公开(公告)号：US20140201504A1

公开(公告)日：2014-07-17

申请号：US14216884

申请日：2014-03-17

Applicant: INTEL CORPORATION

Inventor： Alex Pineiro ,  Thomas D. Fletcher ,  Brian J. Hickmann

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F1/035 ,  G06F9/3895 ,  G06F2101/08 ,  G06F2101/10 ,  G06F2101/12

Abstract: A semiconductor chip is described having a functional unit that can execute a first instruction and execute a second instruction. The first instruction is an instruction that multiplies two operands. The second instruction is an instruction that approximates a function according to C0+C1X2+C2X22. The functional unit has a multiplier circuit. The multiplier circuit has: i) a first input to receive bits of a first operand of the first instruction and receive bits of a C1 term of the second instruction; ii) a second input to receive bits of a second operand of the first instruction and receive bits of a X2 term of the second instruction.

Abstract translation: 描述了具有可执行第一指令并执行第二指令的功能单元的半导体芯片。 第一条指令是将两个操作数相乘的指令。 第二条指令是根据C0 + C1X2 + C2X22近似函数的指令。 功能单元具有乘法电路。 所述乘法器电路具有：i）第一输入，用于接收所述第一指令的第一操作数的比特并接收所述第二指令的C1项的比特; ii）用于接收第一指令的第二操作数的比特并接收第二指令的X2项的比特的第二输入。

公开(公告)号：US09639355B2

公开(公告)日：2017-05-02

申请号：US14216884

申请日：2014-03-17

Applicant: INTEL CORPORATION

Inventor： Alex Pineiro ,  Thomas D. Fletcher ,  Brian J. Hickmann

IPC: G06F1/02 ,  G06F9/30 ,  G06F9/38 ,  G06F1/035

CPC classification number: G06F9/3001 ,  G06F1/035 ,  G06F9/3895 ,  G06F2101/08 ,  G06F2101/10 ,  G06F2101/12

Abstract: A semiconductor chip is described having a functional unit that can execute a first instruction and execute a second instruction. The first instruction is an instruction that multiplies two operands. The second instruction is an instruction that approximates a function according to C0+C1X2+C2X22. The functional unit has a multiplier circuit. The multiplier circuit has: i) a first input to receive bits of a first operand of the first instruction and receive bits of a C1 term of the second instruction; ii) a second input to receive bits of a second operand of the first instruction and receive bits of a X2 term of the second instruction.