公开(公告)号：US09972062B2

公开(公告)日：2018-05-15

申请号：US14550214

申请日：2014-11-21

Applicant: INTEL CORPORATION

Inventor： Alon Gluska ,  Niraj Gupta ,  Mostafa Hagog ,  Dror Reif

IPC: G06F15/80 ,  G09G5/02 ,  G06T1/20

CPC classification number: G06T1/20

Abstract: Flood-fill techniques and architecture are disclosed. In accordance with one embodiment, the architecture comprises a hardware primitive with a software interface which collectively allow for both data-based and task-based parallelism in executing a flood-fill process. The hardware primitive is defined to do the flood-fill function and is scalable and may be implemented with a bitwise definition that can be tuned to meet power/performance targets, in some embodiments. In executing a flood-fill operation, and in accordance with an example embodiment, the software interface produces parallel threads and issues them to processing elements, such that each of the threads can run independently until done. Each processing element in turn accesses a flood-fill hardware primitive, each of which is configured to flood a seed inside an N×M image block. In some cases, processing element commands to the flood-fill hardware primitive(s) can be queued and acted upon pursuant to an arbitration scheme.

公开(公告)号：US20150077422A1

公开(公告)日：2015-03-19

申请号：US14550214

申请日：2014-11-21

Applicant: INTEL CORPORATION

Inventor： Alon Gluska ,  Niraj Gupta ,  Mostafa Hagog ,  Dror Reif

IPC: G06T1/20

CPC classification number: G06T1/20

Abstract: Flood-fill techniques and architecture are disclosed. In accordance with one embodiment, the architecture comprises a hardware primitive with a software interface which collectively allow for both data-based and task-based parallelism in executing a flood-fill process. The hardware primitive is defined to do the flood-fill function and is scalable and may be implemented with a bitwise definition that can be tuned to meet power/performance targets, in some embodiments. In executing a flood-fill operation, and in accordance with an example embodiment, the software interface produces parallel threads and issues them to processing elements, such that each of the threads can run independently until done. Each processing element in turn accesses a flood-fill hardware primitive, each of which is configured to flood a seed inside an N×M image block. In some cases, processing element commands to the flood-fill hardware primitive(s) can be queued and acted upon pursuant to an arbitration scheme.

Abstract translation: 洪水填充技术和结构被公开。 根据一个实施例，该架构包括具有软件接口的硬件原语，该软件接口在执行洪水填充处理时共同允许基于数据和基于任务的并行性。 硬件原语被定义为执行洪水填充功能并且是可扩展的，并且可以在一些实施例中以可以调整以满足功率/性能目标的按位定义来实现。 在执行洪水填充操作时，并且根据示例性实施例，软件接口产生并行线程并将其发布到处理元件，使得每个线程可以独立运行直到完成。 每个处理元件依次访问洪水填充硬件图元，每个填充硬件图元被配置为在N×M图像块内淹没种子。 在某些情况下，根据仲裁方案，可以对洪水填充硬件原语的处理单元命令进行排队和执行。

公开(公告)号：US08902238B2

公开(公告)日：2014-12-02

申请号：US13651854

申请日：2012-10-15

Applicant: Intel Corporation

Inventor： Alon Gluska ,  Niraj Gupta ,  Mostafa Hagog ,  Dror Reif

IPC: G06F15/80 ,  G09G5/02

CPC classification number: G06T1/20

Abstract: Flood-fill techniques and architecture are disclosed. In accordance with one embodiment, the architecture comprises a hardware primitive with a software interface which collectively allow for both data-based and task-based parallelism in executing a flood-fill process. The hardware primitive is defined to do the flood-fill function and is scalable and may be implemented with a bitwise definition that can be tuned to meet power/performance targets, in some embodiments. In executing a flood-fill operation, and in accordance with an example embodiment, the software interface produces parallel threads and issues them to processing elements, such that each of the threads can run independently until done. Each processing element in turn accesses a flood-fill hardware primitive, each of which is configured to flood a seed inside an N×M image block. In some cases, processing element commands to the flood-fill hardware primitive(s) can be queued and acted upon pursuant to an arbitration scheme.

Abstract translation: 洪水填充技术和结构被公开。 根据一个实施例，该架构包括具有软件接口的硬件原语，该软件接口在执行洪水填充处理时共同允许基于数据和基于任务的并行性。 硬件原语被定义为执行洪水填充功能并且是可扩展的，并且可以在一些实施例中以可以调整以满足功率/性能目标的按位定义来实现。 在执行洪水填充操作时，并且根据示例性实施例，软件接口产生并行线程并将其发布到处理元件，使得每个线程可以独立运行直到完成。 每个处理元件依次访问洪水填充硬件图元，每个填充硬件图元被配置为在N×M图像块内淹没种子。 在某些情况下，根据仲裁方案，可以对洪水填充硬件原语的处理单元命令进行排队和执行。