公开(公告)号：US20220114234A1

公开(公告)日：2022-04-14

申请号：US17560100

申请日：2021-12-22

Applicant: INTEL CORPORATION

Inventor： Biji George ,  Sreenivas Subramoney ,  Om Ji Omer ,  Anoop Viswam

IPC: G06F17/16 ,  G06F7/544

Abstract: A matrix processing engine is provided for efficient matrix computation performed by a dense matrix compute circuit (performing SIMD operations) and a scalar computing core (performing SISD operations). These two processing components operate together to produce output data tiles by feeding results of the dense SIMD operations to the scalar computing core using thread packing and an in-line buffer for accumulating and packing the dense result data. This permits the scalar computing to spawn threads to operate on the dense results as available and without requiring partial or intermediate data read/writes between the dense and scalar computations.