公开(公告)号：US20170070242A1

公开(公告)日：2017-03-09

申请号：US15355199

申请日：2016-11-18

Applicant: INTEL CORPORATION

Inventor： Alexander Gendler ,  Gilad Cohen

IPC: H03M13/29 ,  H03M13/13 ,  H03M13/00 ,  G06F11/10

CPC classification number: H03M13/2906 ,  G06F11/1008 ,  H03M13/13 ,  H03M13/616

Abstract: Described is a processor with a data storage structure operative to store data and a first error correction code that corresponds to the data. The processor further includes circuitry to compare the first and second error correction codes to obtain a comparison result. There are no errors in the data when the comparison result is equal to zero and there is at least one error in the data when the comparison result is not equal to zero. The circuitry corrects a single bit error of the data when the comparison result matches one of the unique combination of bit values of one of the plurality of bit groups in the generator matrix and corrects two consecutive data bits of the data when the comparison result corresponds to a predefined number of values as a result of an exclusive-or (XOR) operation performed on two consecutive bit groups of the generator matrix.

Abstract translation: 描述了具有可操作地存储数据的数据存储结构和对应于数据的第一纠错码的处理器。 处理器还包括用于比较第一和第二纠错码以获得比较结果的电路。 当比较结果等于零时，数据中没有错误，并且当比较结果不等于零时，数据中至少有一个错误。 当比较结果与发生器矩阵中的多个位组之一的位值的唯一组合之一匹配时，电路校正数据的单个位错误，并且当比较结果对应于数据时校正数据的两个连续数据位 作为对发生器矩阵的两个连续位组执行异或（XOR）操作的结果的预定数量的值。

公开(公告)号：US09748977B2

公开(公告)日：2017-08-29

申请号：US15355199

申请日：2016-11-18

Applicant: INTEL CORPORATION

Inventor： Alexander Gendler ,  Gilad Cohen

IPC: H03M13/00 ,  H03M13/29 ,  G06F11/10 ,  H03M13/13

CPC classification number: H03M13/2906 ,  G06F11/1008 ,  H03M13/13 ,  H03M13/616

Abstract: Described is a processor with a data storage structure operative to store data and a first error correction code that corresponds to the data. The processor further includes circuitry to compare the first and second error correction codes to obtain a comparison result. There are no errors in the data when the comparison result is equal to zero and there is at least one error in the data when the comparison result is not equal to zero. The circuitry corrects a single bit error of the data when the comparison result matches one of the unique combination of bit values of one of the plurality of bit groups in the generator matrix and corrects two consecutive data bits of the data when the comparison result corresponds to a predefined number of values as a result of an exclusive-or (XOR) operation performed on two consecutive bit groups of the generator matrix.