公开(公告)号：US20170330794A1

公开(公告)日：2017-11-16

申请号：US15528427

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： RAMI HOURANI ,  MARIE KRYSAK ,  FLORIAN GSTREIN ,  RUTH A. BRAIN ,  MARK T. BOHR

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/528

CPC classification number: H01L21/76807 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/528 ,  H01L2221/1031 ,  H01L2221/1063

Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.

公开(公告)号：US20180174893A1

公开(公告)日：2018-06-21

申请号：US15898618

申请日：2018-02-18

Applicant: INTEL CORPORATION

Inventor： RAMI HOURANI ,  MARIE KRYSAK ,  FLORIAN GSTREIN ,  RUTH A. BRAIN ,  MARK T. BOHR

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/31

Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.