公开(公告)号：US20140218088A1

公开(公告)日：2014-08-07

申请号：US13993137

申请日：2011-12-15

Applicant: INTEL CORPORATION

Inventor： Mark Neidengaed ,  Vaughn Grossnickle ,  Nasser Kurd ,  Jeffrey Krieger

IPC: H03K5/04

CPC classification number: H03K5/04 ,  G06F1/04

Abstract: Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period.

Abstract translation: 这里描述了用于重新合成时钟信号的装置，方法和系统。 该装置包括：第一逻辑单元，用于检测输入时钟信号的上升沿，并且用于基于检测到的输入时钟信号的上升沿产生输出时钟信号的上升沿，所述输入时钟信号具有非50 占空比的百分之一和第一期; 以及第二逻辑单元，用于根据检测到的输入时钟信号的上升沿计算输出时钟信号的下降沿，输出时钟信号的下降沿接近第一周期的一半。