公开(公告)号：US20220189976A1

公开(公告)日：2022-06-16

申请号：US17442582

申请日：2019-06-10

Applicant: INTEL CORPORATION

Inventor： Nanda Kumar CHAKRAVARTHI ,  David MEYAARD ,  Abhinav TRIPATHI ,  Liu LIU

IPC: H01L27/11524 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/1157

Abstract: Embodiments of the present disclosure are directed towards a memory device including a top wordline contact located in a region that is protected from erosion during a planarization process, e.g., chemical mechanical polish (CMP). In embodiments, a plurality of wordlines are formed in a stack of multiple layers and a plurality of wordline contacts are formed to intersect with the plurality of wordlines. In embodiments, the stack forms a staircase and each of the plurality of wordline contacts lands on a corresponding each of the wordlines proximate to an edge of the staircase such that a top wordline contact lands in a region on a top wordline previously covered by a sacrificial layer. In some embodiments, the region is proximate to a raised notch at an edge of the staircase. Other embodiments may be described and claimed.