公开(公告)号：US20160276346A1

公开(公告)日：2016-09-22

申请号：US15167006

申请日：2016-05-27

Applicant: INTEL CORPORATION

Inventor： WALID M. HAFEZ ,  PETER J. VANDERVOORN ,  CHIA-HONG JAN

IPC: H01L27/088 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/1608 ,  H01L29/161

Abstract: Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finFET architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed. In some instances, the semiconductor merging layer can be a bridged-epi growth, for example, comprising epitaxial silicon. In some embodiments, such a planar-like device may assist, for example, with analog, high-voltage, wide-Z transistor fabrication. Also, provision of such a planar-like device during a finFET flow may allow for the formation of transistor devices, for example, exhibiting lower capacitance, wider Z, and/or fewer high electric field locations for improved high-voltage reliability, which may make such devices favorable for analog design, in some instances.

Abstract translation: 公开了在finFET制造工艺流程期间在基于鳍片的场效应晶体管（finFET）架构上形成平面状晶体管器件的技术。 在一些实施例中，平面状晶体管可以包括例如半导体层，该半导体层被生长以局部地合并/桥接finFET架构的多个相邻鳍片，并且随后被平坦化以提供高质量的平面表面，平面 形晶体管。 在一些情况下，半导体合并层可以是桥接外延生长，例如包括外延硅。 在一些实施例中，这样的平面状器件可以辅助例如模拟，高电压，宽Z晶体管制造。 此外，在finFET流动期间提供这样的平面状器件可以允许形成晶体管器件，例如，显示出更低的电容，更宽的Z和/或更少的高电场位置，以改善高电压可靠性，其可以 在某些情况下，使这种设备有利于模拟设计。