公开(公告)号：US10114643B2

公开(公告)日：2018-10-30

申请号：US14129531

申请日：2013-05-23

Applicant: INTEL CORPORATION

Inventor： Koichi Yamada ,  Palanivelra Shanmugavelayutham ,  Arvind Krishnaswamy ,  Jason M. Agron ,  Jiwei Lu

IPC: G06F9/30 ,  G06F21/54 ,  G06F12/08 ,  G06F12/0875

Abstract: Various embodiments are generally directed to techniques to detect a return-oriented programming (ROP) attack by verifying target addresses of branch instructions during execution. An apparatus includes a processor component, and a comparison component for execution by the processor component to determine whether there is a matching valid target address for a target address of a branch instruction associated with a translated portion of a routine in a table comprising valid target addresses. Other embodiments are described and claimed.

公开(公告)号：US10055585B2

公开(公告)日：2018-08-21

申请号：US14129246

申请日：2013-08-28

Applicant: INTEL CORPORATION

Inventor： Greg William Dalcher ,  Ravi L. Sahita ,  Palanivelra Shanmugavelayutham ,  Koichi Yamada ,  Arvind Krishnaswamy

IPC: G06F21/54 ,  G06F21/56 ,  G06F21/55

CPC classification number: G06F21/566 ,  G06F21/554

Abstract: Technologies for assembling an execution profile of an event are disclosed. The technologies may include monitoring the event for a branch instruction, generating a callback to a security module upon execution of the branch instruction, filtering the callback according to a plurality of event identifiers, and validating a code segment associated with the branch instruction, the code segment including code executed before the branch instruction and code executed after the branch instruction.