公开(公告)号：US20180253559A1

公开(公告)日：2018-09-06

申请号：US15446995

申请日：2017-03-01

Applicant: INTEL CORPORATION

Inventor： SUDHIR K. SATPATHY ,  VIKRAM B. SURESH ,  SANU K. MATHEW

IPC: G06F21/60 ,  H04L9/06 ,  G06F3/06

CPC classification number: G06F3/0683 ,  G06F21/6209 ,  H04L9/0631 ,  H04L2209/34

Abstract: Various embodiments are generally directed to providing a unified data compression-encryption. In particular, compressed data blocks are secured by encrypting the metadata of the compressed data blocks without the need for encrypting the entire compressed data payload. Selected portions of the payload may be encrypted as desired and identified by using tags that indicate beginning and end of encryption boundaries. In addition, authenticated encryption enables integrity checking at the end of decryption-decompression procedure.

公开(公告)号：US20180183577A1

公开(公告)日：2018-06-28

申请号：US15393196

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： VIKRAM B. SURESH ,  KIRK S. YAP ,  SANU K. MATHEW ,  SUDHIR K. SATPATHY

IPC: H04L9/06 ,  H04L9/32

CPC classification number: H04L9/0643 ,  G09C1/00 ,  H04L2209/125

Abstract: Techniques and computing devices for secure message authentication and, more specifically, but not exclusively, to techniques for unified hardware acceleration of hashing functions, such as SHA-1 and SHA-256 are described. In one embodiment, for example, an apparatus for hardware accelerated hashing in a computer system mat include at least one memory and at least one processor. The apparatus may further include logic comprising at least one adding circuit shared between a first hash function and a second hash function, the logic to perform hardware accelerated hashing of an input message stored in the at least one memory. At least a portion of the logic may be comprised in hardware and executed by the processor to receive the input message to be hashed using the first hash function, perform message expansion of the input message per requirements of the first hash function, perform hashing of the expanded input message over at least four computation rounds, perform, in each of a first, second, and third computation round, more than a single round of computation for the first hash function, and generate a message digest for the input message based upon the first hash function. Other embodiments are described and claimed.

公开(公告)号：US20180097625A1

公开(公告)日：2018-04-05

申请号：US15283323

申请日：2016-10-01

Applicant: INTEL CORPORATION

Inventor： SUDHIR K. SATPATHY ,  RAGHAVAN KUMAR ,  SANU K. MATHEW ,  VIKRAM B. SURESH

IPC: H04L9/30 ,  G09C1/00 ,  G06F7/72

CPC classification number: H04L9/302 ,  G06F7/728 ,  G09C1/00 ,  H04L2209/125

Abstract: Computing devices and techniques for performing modular exponentiation for a data encryption process are described. In one embodiment, for example, an apparatus may include at least one memory logic for an encryption unit to perform encryption according to RSA encryption using a parallel reduction multiplier (PRM) MM process, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one wireless transmitter, the logic to precompute a reduction coefficient, determine an operand product and a reduction product in parallel, the reduction product based on the reduction coefficient, and generate a MM result for the PRM MM process based on the operand product and the reduction product. Other embodiments are described and claimed.