公开(公告)号：US20180374187A1

公开(公告)日：2018-12-27

申请号：US16062511

申请日：2015-12-22

Applicant: INTEL CORPORATION

Inventor： Yao Zu DONG ,  Kun TIAN ,  Tian ZHANG ,  Yulei ZHANG

IPC: G06T1/20 ,  G06F9/48

Abstract: An apparatus and method for best effort quality of service scheduling in a graphics processing architecture. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) to perform graphics processing operations for a plurality of guests; a plurality of buffers to store one or more graphics commands associated with each guest to be executed by the GPU; and a scheduler to evaluate commands in the buffers of a first guest to estimate a cost of executing the commands, the scheduler to select all or a subset of the buffers of the first guest for execution on the GPU based on a determination that the selected buffers can be executed by the GPU within a remaining time slice allocated to the first guest.