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    APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS OF A MATRIX OPERATIONS ACCELERATOR
    4.
    发明公开
    APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS OF A MATRIX OPERATIONS ACCELERATOR 审中-公开

    公开(公告)号：US20240078283A1

    公开(公告)日：2024-03-07

    申请号：US18360793

    申请日：2023-07-27

    Applicant: Intel Corporation

    Inventor： Amit GRADSTEIN ,  Simon RUBANOVICH ,  Sagi MELLER ,  Saeed KHAROUF ,  Gavri BERGER ,  Zeev SPERBER ,  Jose YALLOUZ ,  Ron SCHNEIDER

    IPC: G06F17/16 ,  G06F9/30 ,  G06F9/38

    CPC classification number: G06F17/16 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3851 ,  G06F9/34

    Abstract: Systems, methods, and apparatuses relating to a matrix operations accelerator are described. In one embodiment, a processor includes a matrix operations accelerator circuit that includes a two-dimensional grid of fused multiply accumulate circuits that is switchable to a scheduling mode for execution of a decoded single instruction where the matrix operations accelerator circuit loads a first buffer of the two-dimensional grid of fused multiply accumulate circuits from a first plurality of registers that represents a first input two-dimensional matrix, checks if a second buffer of the two-dimensional grid of fused multiply accumulate circuits stores an immediately prior input two-dimension matrix that is the same as a second input two-dimensional matrix from a second plurality of registers that represents the first input two-dimensional matrix, and when the second buffer of the two-dimensional grid of fused multiply accumulate circuits stores the immediately prior input two-dimension matrix, from execution of a previous instruction, that is the same as the second input two-dimensional matrix: prevents reclamation of the second buffer between execution of the previous instruction and the decoded single instruction, performs an operation on the first input two-dimensional matrix from the first buffer and the immediately prior input two-dimension matrix from the second buffer to produce a resultant, and stores the resultant in resultant storage, and when the second buffer of the two-dimensional grid of fused multiply accumulate circuits does not store the immediately prior input two-dimension matrix, from execution of the previous instruction, that is the same as the second input two-dimensional matrix: loads the second input two-dimensional matrix into the second buffer of the two-dimensional grid of fused multiply accumulate circuits, performs the operation on the first input two-dimensional matrix from the first buffer and the second input two-dimension matrix from the second buffer to produce a resultant, and stores the resultant in the resultant storage.

    BFLOAT16 SCALE AND/OR REDUCE INSTRUCTIONS
    6.
    发明申请
    BFLOAT16 SCALE AND/OR REDUCE INSTRUCTIONS 有权

    公开(公告)号：US20230068781A1

    公开(公告)日：2023-03-02

    申请号：US17463382

    申请日：2021-08-31

    Applicant: Intel Corporation

    Inventor： Menachem ADELMAN ,  Alexander HEINECKE ,  Robert VALENTINE ,  Zeev SPERBER ,  Amit GRADSTEIN ,  Mark CHARNEY ,  Evangelos GEORGANAS ,  Dhiraj KALAMKAR ,  Christopher HUGHES ,  Cristina ANDERSON

    IPC: G06F9/30

    Abstract: Techniques for scale and reduction of BF16 data elements are described. An exemplary instruction includes fields for an having fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operands, a floating point scale operation of a BF16 data element of the first packed data source by multiplying the data element by a power of 2 value, wherein a value of the exponent of the power of 2 value is a floor value of a BF16 data element of the second packed data source, and store a result of the floating point scale operation into a corresponding data element position of the packed data destination operand.

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