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公开(公告)号：US20250021308A1
公开(公告)日：2025-01-16
申请号：US18221127
申请日：2023-07-12
Applicant: Wisconsin Alumni Research Foundation
Inventor： Joshua San Miguel , Di Wu , Zhewen Pan
Abstract: A computer architecture for computing products and sums of products applies one multiplicand to an accumulator which produces a successive set of product values which may be captured by a capture signal delayed in time according to the second operand. Multiple capture signals from different multipliers can simultaneously make use of the accumulated value allowing value reuse, speeding the calculation of vector and matrix calculations having many identical operands.
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公开(公告)号：US12147547B2
公开(公告)日：2024-11-19
申请号：US17429780
申请日：2019-02-12
Applicant: NEC Corporation
Inventor： Hikaru Tsuchida , Toshinori Araki , Kazuma Ohara , Takuma Amada
Abstract: The information processing apparatus comprises a basic operation seed storage part, a reshare value computation part, and a share construction part. The basic operation seed storage part stores a seed for generating a random number used when computation is performed on a share. The reshare value computation part generates a random number using the seed, computes a share reshare value using the generated random number, and transmits data regarding the generated random number to other apparatuses. The share construction part constructs a share for type conversion using the data regarding the generated random number and the share reshare value received from other apparatuses.
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公开(公告)号：US20240281214A1
公开(公告)日：2024-08-22
申请号：US18439297
申请日：2024-02-12
Applicant: STMicroelectronics International N.V.
Inventor： Thierry SIMON
CPC classification number: G06F7/764 , H04L9/3066 , H04L2209/046
Abstract: A method includes performing a cryptographic operation using a processing device. The performing the cryptographic operation includes protecting the performing of the cryptographic operation against side channel attacks by selecting a value amongst two values based on a selection bit. Selecting the value includes concatenating the two values in a register, generating a concatenated word including the two values in two distinct portions of the concatenated word in the register. The concatenated word is rotated according to the value of the selection bit to position the selected value in a determined portion of the concatenated word in the register amongst said two portions. The unselected value in the concatenated word is suppressed. One or more processing operations is performed based on a result of the cryptographic operation.
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公开(公告)号：US20240192924A1
公开(公告)日：2024-06-13
申请号：US18503494
申请日：2023-11-07
Applicant: NXP B.V.
Inventor： Alexandre Venelli , Francois Dassance
Abstract: Shuffling and sliding subgroup techniques are provided to shuffle an order of a plurality of data blocks. The techniques include selecting a first value for a starting position and a second value for a step size. A first iteration of the technique includes generating a first subgroup to include a first subset of the plurality of data blocks based on the first value and the second value and executing data operations associated therewith. Then, in each of one or more subsequent iterations based on whether all of the data blocks have been added to the shuffled order, subsequent subgroups are added to the shuffled order that each include a different subset of the plurality of data blocks that are shifted by one position from data blocks in the previously generated subgroup and executing data operations associated therewith.
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公开(公告)号：US20240134604A1
公开(公告)日：2024-04-25
申请号：US18396423
申请日：2023-12-26
Applicant: Intel Corporation
Inventor： Theo Drane , Christopher Louis Poole , William Zorn , Emiliano Morini
CPC classification number: G06F7/501 , G06F7/5057 , G06F7/768
Abstract: Described herein is a generalized optimal reduction scheme for reducing an array modulo a constant. The constant modulo operation calculates a result for array of bits xi, width n modulo an odd positive integer constant d, (e.g., x[n:0] mod d). Circuitry to perform such operation can be configured to compress the array of bits xi, width n into an array of bits yi width m. The techniques described herein enable the design of optimal circuitry via iterative exploration of all potential reduction strategies that are available given the input constraints.
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Patent Agency Ranking
公开(公告)号：US11966717B2
公开(公告)日：2024-04-23
申请号：US17652001
申请日：2022-02-22
Applicant: AUTEL INTELLIGENT TECHNOLOGY CORP., LTD.
Inventor： Chu Jiang
CPC classification number: G06F7/764 , G06F7/5443 , H04L12/40 , H04L2012/40215
Abstract: A (controller area network) CAN filter combining method and a CNA controller are provided. The CAN filter includes a special filter and one or more common filters. The method includes: initializing a mask code and at least two filter codes of the special filter, acquiring a first total number of the filter codes in the special filter and a second total number of the common filters, acquiring mask codes and filter codes of the common filters, and adjusting the mask code and the filter codes of the special filter on the basis of the first total number, the second total number, and the mask codes and the filtering codes of all of the common filters. The method reduces the load of a processor, and prevents the CAN controller from processing a large amount of irrelevant data, thereby accelerating communications.
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公开(公告)号：US20240103812A1
公开(公告)日：2024-03-28
申请号：US18275121
申请日：2021-02-03
Applicant: NEC Corporation
Inventor： Shinji Ito
IPC: G06F7/76
CPC classification number: G06F7/76
Abstract: To enable selection of useful vector sequence a1,a2, . . . ,aT in a bandit linear optimization algorithm for which a fixed strategy is ineffective, an information processing apparatus (1) includes a vector selection unit (11) that selects a vector at in each round t∈[T] (T is any natural number) from a subset A of a d-dimensional vector space Rd (d is any natural number). The vector selection unit (11) uses l1,l2, . . . ,lT∈Rd as loss vectors to select the vector at in each round t such that an asymptotic behavior of an expected value of tracking regret R(u)=Σt∈[T]ltTat−Σt∈[T]ltTut with respect to any comparative vector sequence u1,u2, . . . ,uT∈A or an asymptotic behavior ignoring logarithmic factors of the expected value of the tracking regret R(u) is constrained from above by a preset function A(d,T,P), where P is a natural number not less than 1 given by P=|{t∈[T−1]|ut≠ut+1}|.
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公开(公告)号：US11922133B2
公开(公告)日：2024-03-05
申请号：US17038774
申请日：2020-09-30
Inventor： Rene Peyrard , Fabrice Romain , Jean-Michel Derien , Christophe Eichwald
Abstract: A method includes processing, by an arithmetic and logic unit of a processor, masked data, and keeping, by the arithmetic and logic unit of the processor, the masked data masked throughout their processing by the arithmetic and logic unit. A processor includes an arithmetic and logic unit configured to keep masked data masked throughout processing of the masked data in the arithmetic and logic unit.
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公开(公告)号：US11902706B2
公开(公告)日：2024-02-13
申请号：US17708003
申请日：2022-03-30
Inventor： Jianxiong Xiao
CPC classification number: H04N7/04
Abstract: A method for transmitting high bandwidth camera data through a SerDes links is provided. The method includes steps of: calculating transmission bandwidth required for transmitting image data, and the image data is obtained by a high bandwidth camera; determining a maximum bandwidth capacity of each SerDes link of a plurality of SerDes links; cutting the image data into a plurality of sub images according to the transmission bandwidth and the maximum bandwidth capacity of each SerDes link; assigning each sub image to a sub image transmission area in a corresponding SerDes link, and each SerDes link containing the sub image transmission area and the sub image reception area; acquiring a plurality of sub images transmitted in the plurality of the SerDes links from the corresponding sub image reception area; and splicing the plurality of sub images into the image data.
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10.发明公开公开(公告)号：US20240045722A1
公开(公告)日：2024-02-08
申请号：US18488674
申请日：2023-10-17
Applicant: NVIDIA Corporation
Inventor： Ravi P. Singh , Ching-Yu Hung , Jagadeesh Sankaran , Ahmad Itani , Yen-Te Shih
CPC classification number: G06F9/5027 , G06F7/76 , G06F1/03 , G06F9/5077
Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.
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