公开(公告)号：US20200043874A1

公开(公告)日：2020-02-06

申请号：US16051376

申请日：2018-07-31

Applicant: INTEL IP CORPORATION

Inventor： Daniel Sira ,  Domagoj Siprak ,  Jonas Fritzin

IPC: H01L23/66 ,  G06F17/50 ,  H01L49/02 ,  H01L23/522 ,  H01L23/482 ,  H01L27/06

Abstract: An integrated circuit structure includes a first metallization layer with first and second electrodes, each of which has electrode fingers. A second metallization layer may be included below the first metallization layer and include one or more electrodes with electrode fingers. The integrated circuit structure is configured to exhibit at least partial vertical inductance cancellation when the first electrode and second electrode are energized. The integrated circuit structure can be configured to also exhibit horizontal inductance cancellation between adjacent electrode fingers. Also disclosed is a simulation model that includes a capacitor model that models capacitance between electrode fingers having a finger length and includes at least one resistor-capacitor series circuit in which a resistance of the resistor increases with decreasing finger length for at least some values of the finger length.