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公开(公告)号：US20180076708A1
公开(公告)日：2018-03-15
申请号：US15263466
申请日：2016-09-13
Applicant: International Business Machines Corporation
Inventor： John F. Bulzacchelli , Michael A. Sperling , Zeynep Toprak Deniz
IPC: H02M3/07
Abstract: A distributed voltage regulator includes multiple micro-regulators disposed in a corresponding set of circuit sectors of an integrated circuit. Each micro-regulator provides current to the corresponding circuit sector at a current injection point. The regulator also includes a control module configured to receive feedback signals corresponding to a one or more sense points within each circuit sector and provide a control signal to each micro-regulator. The control module limits load-sharing imbalance within the plurality of micro-regulators. A voltage regulator with multiple sense points includes a micro-regulator that provides current at a current injection point, and a control module that receives feedback signals corresponding to a plurality of sense points and provides a control signal to the micro-regulator. The micro-regulator may comprise a charge pump that provides a local reference voltage that enables the micro-regulator to suppress local voltage drooping during feedback transitions (e.g., while switching between different feedback signals).
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公开(公告)号：US20150061744A1
公开(公告)日：2015-03-05
申请号：US14458428
申请日：2014-08-13
Applicant: International Business Machines Corporation
Inventor： John F. Bulzacchelli , Zeynep Toprak Deniz , Joshua D. Friedrich , Tilman Gloekler , Gregory S. Still
IPC: G05F1/625
Abstract: Systems and methods are provided to regulate a supply voltage of a load circuit. For example, a system includes a voltage regulator circuit that includes a passgate device. The system includes a passgate strength calibration control module which is configured to (i) obtain information which specifies operating conditions of the voltage regulator circuit, (ii) access entries of one or more look-up tables using the obtained information, (iii) use information within the accessed entries to determine a maximum load current that could be demanded by the load circuit under the operating conditions specified by the obtained information, and to predict a passgate device width which is sufficient to supply the determined maximum load current, and (iv) set an active width of the passgate device according to the predicted passgate device width.
Abstract translation: 提供系统和方法来调节负载电路的电源电压。 例如，系统包括包括通路装置的电压调节器电路。 该系统包括通道强度校准控制模块，其被配置为（i）获得指定电压调节器电路的操作条件的信息，（ii）使用获得的信息访问一个或多个查找表的访问条目，（iii）使用 在所访问的条目内的信息以确定由所获得的信息指定的操作条件下负载电路可能要求的最大负载电流，并且预测足以提供所确定的最大负载电流的通道装置宽度，以及（iv ）根据预测的通道装置宽度设置通道装置的有效宽度。
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公开(公告)号：US08981829B1
公开(公告)日：2015-03-17
申请号：US14458428
申请日：2014-08-13
Applicant: International Business Machines Corporation
Inventor： John F. Bulzacchelli , Zeynep Toprak Deniz , Joshua D. Friedrich , Tilman Gloekler , Gregory S. Still
Abstract: Systems and methods are provided to regulate a supply voltage of a load circuit. For example, a system includes a voltage regulator circuit that includes a passgate device. The system includes a passgate strength calibration control module which is configured to (i) obtain information which specifies operating conditions of the voltage regulator circuit, (ii) access entries of one or more look-up tables using the obtained information, (iii) use information within the accessed entries to determine a maximum load current that could be demanded by the load circuit under the operating conditions specified by the obtained information, and to predict a passgate device width which is sufficient to supply the determined maximum load current, and (iv) set an active width of the passgate device according to the predicted passgate device width.
Abstract translation: 提供系统和方法来调节负载电路的电源电压。 例如，系统包括包括通路装置的电压调节器电路。 该系统包括通道强度校准控制模块，其被配置为（i）获得指定电压调节器电路的操作条件的信息，（ii）使用获得的信息访问一个或多个查找表的访问条目，（iii）使用 在所访问的条目内的信息以确定由所获得的信息指定的操作条件下负载电路可能要求的最大负载电流，并且预测足以提供所确定的最大负载电流的通道装置宽度，以及（iv ）根据预测的通道装置宽度设置通道装置的有效宽度。
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公开(公告)号：US10033270B2
公开(公告)日：2018-07-24
申请号：US15334385
申请日：2016-10-26
Applicant: International Business Machines Corporation
Inventor： John F. Bulzacchelli , Seongwon Kim , Michael A. Sperling , Zeynep Toprak Deniz
Abstract: An apparatus for providing a local reference voltage for a voltage regulator includes a reference capacitor configured to provide the local reference voltage, a charge pump configured to push current to, or pull current from, the reference capacitor according to one or more control inputs received by the charge pump, and a boosting circuit configured to add or subtract a discrete quantity of charge to the reference capacitor according to one or more boosting control signals. A boosting control circuit may be configured to disconnect a boosting capacitor from the reference capacitor during a first phase of a control cycle and connect the boosting capacitor to the reference capacitor during a second phase of the control cycle. The boosting capacitor may be pre-charged (to add charge) or discharged (to subtract charge) during the first phase of the control cycle. A corresponding method is also disclosed herein.
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公开(公告)号：US20150123633A1
公开(公告)日：2015-05-07
申请号：US14595850
申请日：2015-01-13
Applicant: International Business Machines Corporation
Inventor： John F. Bulzacchelli , Zeynep Toprak Deniz , Joshua D. Friedrich , Tilman Gloekler , Gregory S. Still
IPC: G05F1/59
Abstract: Systems and methods are provided to regulate a supply voltage of a load circuit. For example, a system includes a voltage regulator circuit that includes a passgate device. The system includes a passgate strength calibration control module which is configured to (i) obtain information which specifies operating conditions of the voltage regulator circuit, (ii) access entries of one or more look-up tables using the obtained information, (iii) use information within the accessed entries to determine a maximum load current that could be demanded by the load circuit under the operating conditions specified by the obtained information, and to predict a passgate device width which is sufficient to supply the determined maximum load current, and (iv) set an active width of the passgate device according to the predicted passgate device width.
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Patent Agency Ranking
公开(公告)号：US08755428B2
公开(公告)日：2014-06-17
申请号：US13763312
申请日：2013-02-08
Applicant: International Business Machines Corporation
Inventor： Ankur Agrawal , John F. Bulzacchelli , Daniel J. Friedman , Zeynep Toprak Deniz
IPC: H04B17/00
CPC classification number: H04L25/03878 , H03K5/135 , H03K2005/00052 , H03K2005/00065 , H04L27/01
Abstract: Circuits and methods are provided for efficient feed-forward equalization when sample-and-hold circuitry is employed to generate n time-delayed versions of an input data signal to be equalized. To equalize the input data signal, m data signals are input to m feed-forward equalization (FFE) taps of a current-integrating summer circuit, wherein each of the m data signals corresponds to one of the n time-delayed versions of the input data signal. A capacitance is precharged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each of the m FFE taps during an integration period of the current-integrating summer circuit, wherein the output currents from the m FFE taps collectively charge or discharge the capacitance during the integration period. A gating control signal is applied to an FFE tap during the integration period to disable the FFE tap during a portion of the integration period in which the data signal input to the FFE tap is invalid.
Abstract translation: 提供电路和方法用于当采样和保持电路用于产生待均衡的输入数据信号的n个时间延迟版本时的有效的前馈均衡。 为了均衡输入数据信号，将m个数据信号输入到电流积分加法电路的前馈均衡（FFE）抽头，其中每个m个数据信号对应于输入的n个时间延迟版本之一 数据信号。 在积分电路的夏季电路的复位期间，将电容预先充电至预充电电平。 在积分积分期间电路的积分期间，由m FFE抽头中的每一个产生输出电流，其中来自m FFE抽头的输出电流在积分期间共同对电容进行充电或放电。 在积分期间，门控控制信号被施加到FFE抽头，以在输入到FFE抽头的数据信号无效的积分周期的一部分期间禁用FFE抽头。
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公开(公告)号：US10069409B2
公开(公告)日：2018-09-04
申请号：US15263466
申请日：2016-09-13
Applicant: International Business Machines Corporation
Inventor： John F. Bulzacchelli , Michael A. Sperling , Zeynep Toprak Deniz
Abstract: A distributed voltage regulator includes multiple micro-regulators disposed in a corresponding set of circuit sectors of an integrated circuit. Each micro-regulator provides current to the corresponding circuit sector at a current injection point. The regulator also includes a control module configured to receive feedback signals corresponding to a one or more sense points within each circuit sector and provide a control signal to each micro-regulator. The control module limits load-sharing imbalance within the plurality of micro-regulators. A voltage regulator with multiple sense points includes a micro-regulator that provides current at a current injection point, and a control module that receives feedback signals corresponding to a plurality of sense points and provides a control signal to the micro-regulator. The micro-regulator may comprise a charge pump that provides a local reference voltage that enables the micro-regulator to suppress local voltage drooping during feedback transitions (e.g., while switching between different feedback signals).
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公开(公告)号：US20150054575A1
公开(公告)日：2015-02-26
申请号：US14502228
申请日：2014-09-30
Applicant: International Business Machines Corporation
Inventor： John F. Bulzacchelli , Paul D. Muench , Michael A. Sperling , Zeynep Toprak Deniz
IPC: G05F1/10
Abstract: A system and method to regulate voltage on a chip are described. The system includes a central controller to output a digital code based on a voltage measurement from a sense point on a power grid of the chip. The system also includes a plurality of micro-regulators, each of the plurality of micro-regulators outputting a respective voltage to the power grid based on the digital code.
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公开(公告)号：US08913655B2
公开(公告)日：2014-12-16
申请号：US13968810
申请日：2013-08-16
Applicant: International Business Machines Corporation
Inventor： Ankur Agrawal , John F. Bulzacchelli , Daniel J. Friedman , Zeynep Toprak Deniz
CPC classification number: H04L25/03878 , H03K5/135 , H03K2005/00052 , H03K2005/00065 , H04L27/01
Abstract: Circuits and methods are provided for efficient feed-forward equalization when sample-and-hold circuitry is employed to generate n time-delayed versions of an input data signal to be equalized. To equalize the input data signal, m data signals are input to m feed-forward equalization (FFE) taps of a current-integrating summer circuit, wherein each of the m data signals corresponds to one of the n time-delayed versions of the input data signal. A capacitance is precharged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each of the m FFE taps during an integration period of the current-integrating summer circuit, wherein the output currents from the m FFE taps collectively charge or discharge the capacitance during the integration period. A gating control signal is applied to an FFE tap during the integration period to disable the FFE tap during a portion of the integration period in which the data signal input to the FFE tap is invalid.
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公开(公告)号：US20130336378A1
公开(公告)日：2013-12-19
申请号：US13968810
申请日：2013-08-16
Applicant: International Business Machines Corporation
Inventor： Ankur Agrawal , John F. Bulzacchelli , Daniel J. Friedman , Zeynep Toprak Deniz
IPC: H04L25/03
CPC classification number: H04L25/03878 , H03K5/135 , H03K2005/00052 , H03K2005/00065 , H04L27/01
Abstract: Circuits and methods are provided for efficient feed-forward equalization when sample-and-hold circuitry is employed to generate n time-delayed versions of an input data signal to be equalized. To equalize the input data signal, m data signals are input to m feed-forward equalization (FFE) taps of a current-integrating summer circuit, wherein each of the m data signals corresponds to one of the n time-delayed versions of the input data signal. A capacitance is precharged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each of the m FFE taps during an integration period of the current-integrating summer circuit, wherein the output currents from the m FFE taps collectively charge or discharge the capacitance during the integration period. A gating control signal is applied to an FFE tap during the integration period to disable the FFE tap during a portion of the integration period in which the data signal input to the FFE tap is invalid.
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