-
公开(公告)号：US20190097618A1
公开(公告)日：2019-03-28
申请号：US15854961
申请日：2017-12-27
Applicant: International Business Machines Corporation
Inventor： Michael Koch , Matthias Ringe , Andreas Arp , Fatih Cilek
CPC classification number: H03K5/1565 , H03K5/133 , H03K21/08 , H03K2005/00065 , H03K2005/00071
Abstract: The present invention provides a system and method of correcting duty cycle (DC) and compensating for active clock edge shift. In an embodiment, the system includes at least one control circuit to receive DCC control signals and to output at least one first adjustment signal, at least one second adjustment signal, at least one first correction signal, and at least one second correction signal, at least one adjustment circuit to change a DC value of an input clock signal, at least one correction circuit to compensate for a shift of an active clock edge of the input clock signal, and where one of the at least one adjustment circuit and the at least one correction circuit is to receive the input clock signal and wherein one of the at least one adjustment circuit and the at least one correction circuit is to transmit a corrected output clock signal.
-
公开(公告)号：US09698970B1
公开(公告)日：2017-07-04
申请号：US15060342
申请日：2016-03-03
Applicant: Xilinx, Inc.
Inventor： Junho Cho
CPC classification number: H03K5/135 , H03K5/131 , H03K5/14 , H03K2005/00052 , H03K2005/00065 , H03K2005/00071 , H03L7/081
Abstract: An example clock delivery system includes a phase-locked loop (PLL) configured to generate a plurality of input clocks, a phase interpolator configured to receive the plurality of input clocks and generate a plurality of output clocks, and a clock data recovery (CDR) circuit configured to receive the plurality of output clocks. The phase interpolator includes a decoder having a plurality of inputs configured to receive binary codes and a respective plurality of outputs configured to output thermometer codes, and a mixer circuitry segmented into a plurality of unit circuits that are enabled or disabled based on bits of the thermometer codes.
-
3.发明授权Timing generator for generating high resolution pulses having arbitrary widths 有权用于产生具有任意宽度的高分辨率脉冲的定时发生器公开(公告)号：US09584105B1
公开(公告)日：2017-02-28
申请号：US15066182
申请日：2016-03-10
Applicant: ANALOG DEVICES, INC.
Inventor： David P. Foley
CPC classification number: H03K5/133 , H03K5/134 , H03K2005/00019 , H03K2005/00065 , H03L7/0816
Abstract: An exemplary timing generator includes a coarse delay circuit configured to generate a coarse delayed rising edge signal and a coarse delayed falling edge signal from a reference timing signal; a fine delay circuit configured to generate a fine delayed rising edge signal from the coarse delayed rising edge signal and a fine delayed falling edge signal from the coarse delayed falling edge signal; an edge combiner configured to generate the timing signal based on the fine delayed rising edge signal and the fine delayed falling edge signal; and a masking circuit configured to generate a rising edge masking signal and a falling edge masking signal for controlling when the rising edges and the falling edges of the timing signal are generated.
Abstract translation: 示例性定时发生器包括：粗延迟电路，被配置为从参考定时信号产生粗延迟上升沿信号和粗延迟下降沿信号; 配置为从粗延迟上升沿信号和粗延迟下降沿信号产生精细延迟下降沿信号的精细延迟上升沿信号; 边缘组合器，被配置为基于所述精细延迟上升沿信号和精细延迟下降沿信号产生定时信号; 以及掩蔽电路，被配置为产生上升沿屏蔽信号和下降沿屏蔽信号，用于控制何时产生定时信号的上升沿和下降沿。
-
公开(公告)号：US09407248B2
公开(公告)日：2016-08-02
申请号：US14833972
申请日：2015-08-24
Applicant: Laurence H. Cooke
Inventor： Laurence H. Cooke
CPC classification number: H03K5/15 , H03K5/131 , H03K5/133 , H03K5/15013 , H03K2005/00065 , H03K2005/00247
Abstract: A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-fop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.
Abstract translation: 由可变电阻器元件组成的存储器状结构，用于调整时钟分配结构的相应分支和叶片，其可用于补偿逐芯片和/或组合逻辑逐个路径延迟变化，其中 可能是因为例如深亚微米器件和互连中的物理变化。 还提供了具有执行延迟测试测量功能的单个系统时钟扫描触发器。 还提出了用于测量组合逻辑路径延迟以确定最大时钟频率和编程可变电阻器的延迟的方法，以及用于校准和测量编程的可变电阻器的方法。
-
公开(公告)号：US20160094239A1
公开(公告)日：2016-03-31
申请号：US14848924
申请日：2015-09-09
Applicant: Renesas Electronics Corporation
Inventor： Masaki FUJIWARA , Yasuo MORIMOTO , Takashi MATSUMOTO
CPC classification number: H03M1/125 , H03K5/133 , H03K2005/00065 , H03M1/12 , H03M1/38 , H03M1/46 , H03M1/462 , H03M1/468
Abstract: A semiconductor device capable of accurately controlling the cycle of an internal clock signal. This semiconductor device, by using signal that is output from a sequence register of an asynchronous successive approximation type ADC when N times of comparison are completed, detects whether or not the signal and its delay signal are output when the period transitions from a comparison period to a sampling period, and generates, on the basis of the detection result, a delay control signal for controlling the cycle of an internal clock signal by controlling the delay times of the delay circuits.
Abstract translation: 能够精确地控制内部时钟信号的周期的半导体器件。 当N次比较完成时，通过使用从异步逐次逼近型ADC的序列寄存器输出的信号，该半导体器件检测当该周期从比较期间转变到该时间段时是否输出信号及其延迟信号 并根据检测结果生成用于通过控制延迟电路的延迟时间来控制内部时钟信号的周期的延迟控制信号。
-
Patent Agency Ranking
公开(公告)号：US20150365082A1
公开(公告)日：2015-12-17
申请号：US14833972
申请日：2015-08-24
Applicant: Laurence H. COOKE
Inventor： Laurence H. COOKE
IPC: H03K5/15
CPC classification number: H03K5/15 , H03K5/131 , H03K5/133 , H03K5/15013 , H03K2005/00065 , H03K2005/00247
Abstract: A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-fop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.
Abstract translation: 由可变电阻器元件组成的存储器状结构，用于调整时钟分配结构的相应分支和叶片，其可用于补偿逐芯片和/或组合逻辑逐个路径延迟变化，其中 可能是因为例如深亚微米器件和互连中的物理变化。 还提供了具有执行延迟测试测量能力的单个系统时钟扫描触发器。 还提出了用于测量组合逻辑路径延迟以确定最大时钟频率和编程可变电阻器的延迟的方法，以及用于校准和测量编程的可变电阻器的方法。
-
公开(公告)号：US08913655B2
公开(公告)日：2014-12-16
申请号：US13968810
申请日：2013-08-16
Applicant: International Business Machines Corporation
Inventor： Ankur Agrawal , John F. Bulzacchelli , Daniel J. Friedman , Zeynep Toprak Deniz
CPC classification number: H04L25/03878 , H03K5/135 , H03K2005/00052 , H03K2005/00065 , H04L27/01
Abstract: Circuits and methods are provided for efficient feed-forward equalization when sample-and-hold circuitry is employed to generate n time-delayed versions of an input data signal to be equalized. To equalize the input data signal, m data signals are input to m feed-forward equalization (FFE) taps of a current-integrating summer circuit, wherein each of the m data signals corresponds to one of the n time-delayed versions of the input data signal. A capacitance is precharged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each of the m FFE taps during an integration period of the current-integrating summer circuit, wherein the output currents from the m FFE taps collectively charge or discharge the capacitance during the integration period. A gating control signal is applied to an FFE tap during the integration period to disable the FFE tap during a portion of the integration period in which the data signal input to the FFE tap is invalid.
-
公开(公告)号：US20130336378A1
公开(公告)日：2013-12-19
申请号：US13968810
申请日：2013-08-16
Applicant: International Business Machines Corporation
Inventor： Ankur Agrawal , John F. Bulzacchelli , Daniel J. Friedman , Zeynep Toprak Deniz
IPC: H04L25/03
CPC classification number: H04L25/03878 , H03K5/135 , H03K2005/00052 , H03K2005/00065 , H04L27/01
Abstract: Circuits and methods are provided for efficient feed-forward equalization when sample-and-hold circuitry is employed to generate n time-delayed versions of an input data signal to be equalized. To equalize the input data signal, m data signals are input to m feed-forward equalization (FFE) taps of a current-integrating summer circuit, wherein each of the m data signals corresponds to one of the n time-delayed versions of the input data signal. A capacitance is precharged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each of the m FFE taps during an integration period of the current-integrating summer circuit, wherein the output currents from the m FFE taps collectively charge or discharge the capacitance during the integration period. A gating control signal is applied to an FFE tap during the integration period to disable the FFE tap during a portion of the integration period in which the data signal input to the FFE tap is invalid.
-
公开(公告)号：US08558597B2
公开(公告)日：2013-10-15
申请号：US13538621
申请日：2012-06-29
Applicant: Ankur Agrawal , John F. Bulzacchelli , Sergey V. Rylov
Inventor： Ankur Agrawal , John F. Bulzacchelli , Sergey V. Rylov
IPC: H03H11/16
CPC classification number: H04L25/03878 , H03K5/135 , H03K2005/00052 , H03K2005/00065 , H04L27/01
Abstract: A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.
-
公开(公告)号：US20130207708A1
公开(公告)日：2013-08-15
申请号：US13538621
申请日：2012-06-29
Applicant: Ankur Agrawal , John F. Bulzacchelli , Sergey V. Rylov
Inventor： Ankur Agrawal , John F. Bulzacchelli , Sergey V. Rylov
IPC: H03K5/13
CPC classification number: H04L25/03878 , H03K5/135 , H03K2005/00052 , H03K2005/00065 , H04L27/01
Abstract: A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.
Abstract translation: 提供了相位插值器电路，其通过在第一和第二时钟信号的相位之间进行内插来产生输出时钟信号。 通过检测第一时钟信号的边沿并施加第一电流来将输出节点的电容充电至小于或等于电压比较器的切换阈值的电压电平，并且检测第 第二时钟信号，并且施加第二电流以将输出节点的电容充电到超过电压比较器的切换阈值的电压电平。 改变第一电流的大小以调节输出节点的电容被充电到超过电压比较器的切换阈值的电压电平的时刻，并调整从电压比较器输出的输出时钟信号的相位 。
-
-
-
-
-
-
-
-
-
Search Results
261
records
(took 0.02 seconds)
