公开(公告)号：US08300660B2

公开(公告)日：2012-10-30

申请号：US12697245

申请日：2010-01-30

申请人： Ichiro Yokokura ,  Hiromichi Makishima ,  Shinji Sawane

发明人： Ichiro Yokokura ,  Hiromichi Makishima ,  Shinji Sawane

IPC分类号： H04J3/22

CPC分类号： H04J3/0623

摘要： A transmitting apparatus includes a detecting unit that detects deviation and balance relative to a specified bit rate of a frame signal input at a constant bit rate; a dividing unit that reads at constant intervals from a buffer storing the frame signal and outputs a signal divided into a plurality of segments having a predetermined data length; and a correcting unit that, based on the deviation and balance detected by the detecting unit, corrects the data length for the division by the dividing unit.

摘要翻译： 发送装置包括检测单元，其检测相对于以恒定比特率输入的帧信号的指定比特率的偏差和平衡; 分割单元，从存储帧信号的缓冲器以恒定的间隔读取，并输出分割成具有预定数据长度的多个段的信号; 以及校正单元，其基于由所述检测单元检测到的偏差和平衡来校正由所述分割单元划分的数据长度。

公开(公告)号：US20100238954A1

公开(公告)日：2010-09-23

申请号：US12697245

申请日：2010-01-30

申请人： Ichiro YOKOKURA ,  Hiromichi Makishima ,  Shinji Sawane

发明人： Ichiro YOKOKURA ,  Hiromichi Makishima ,  Shinji Sawane

IPC分类号： H04J3/22

CPC分类号： H04J3/0623

摘要： A transmitting apparatus includes a detecting unit that detects deviation and balance relative to a specified bit rate of a frame signal input at a constant bit rate; a dividing unit that reads at constant intervals from a buffer storing the frame signal and outputs a signal divided into a plurality of segments having a predetermined data length; and a correcting unit that, based on the deviation and balance detected by the detecting unit, corrects the data length for the division by the dividing unit.

摘要翻译： 发送装置包括检测单元，其检测相对于以恒定比特率输入的帧信号的指定比特率的偏差和平衡; 分割单元，从存储帧信号的缓冲器以恒定的间隔读取，并输出分割成具有预定数据长度的多个段的信号; 以及校正单元，其基于由所述检测单元检测到的偏差和平衡来校正由所述分割单元划分的数据长度。

公开(公告)号：US20070245176A1

公开(公告)日：2007-10-18

申请号：US11502517

申请日：2006-08-11

申请人： Shinji Sawane ,  Yuji Obana ,  Hiroyuki Kitajima

发明人： Shinji Sawane ,  Yuji Obana ,  Hiroyuki Kitajima

IPC分类号： G06F11/00

CPC分类号： H04L1/0061 ,  H04L1/203

摘要： In a BER monitoring circuit, error cycles of input data are detected by a parity check portion and an error cycle detecting portion, a maximum (average/median) value is detected from among the error cycles by an error cycle memory and an error cycle maximum (average/median) value retrieving portion. The value is converted into a corresponding estimated error rate by a Te-BER conversion table and an alarm is generated by an SF/SD detecting -portion when the estimated error rate exceeds an alarm detecting threshold. Thereafter, the alarm is released when the estimated error rate assumes equal to or less than an alarm releasing threshold. Also, an error-free detecting portion is activated when an alarm is generated and releases the alarm when a time period for which the error cycles stay flat exceeds a cycle corresponding to the alarm releasing threshold.

摘要翻译： 在BER监视电路中，通过奇偶校验部分和错误周期检测部分检测输入数据的错误周期，通过错误周期存储器和错误周期最大值检测错误周期中的最大值（平均值/中值） （平均/中值）检索部分。 当估计的误码率超过警报检测阈值时，该值被转换表转换成相应的估计错误率，并通过SF / SD检测产生警报。 此后，当估计误差率等于或小于报警释放阈值时，报警被释放。 此外，当产生报警时，无错误检测部分被激活，并且当错误周期保持平坦的时间段超过与报警释放阈值相对应的周期时，释放报警。