公开(公告)号：US20130061016A1

公开(公告)日：2013-03-07

申请号：US13605880

申请日：2012-09-06

申请人： Ignazio Antonino Urzi ,  Nicolas Graciannette

发明人： Ignazio Antonino Urzi ,  Nicolas Graciannette

IPC分类号： G06F12/00 ,  G06F12/14

CPC分类号： G06F21/79

摘要： A first engine and a memory access controller are each configured to receive memory operation information in parallel. In response to receiving the memory operation information, the first engine is prepared to perform a function on memory data associated with the memory operation and the memory controller is configured to prepare the memory to cause the memory operation to be performed.

摘要翻译： 第一引擎和存储器访问控制器各自被配置为并行地接收存储器操作信息。 响应于接收到存储器操作信息，第一引擎准备执行与存储器操作相关联的存储器数据的功能，并且存储器控制器被配置为准备存储器以使得执行存储器操作。

公开(公告)号：US07302601B2

公开(公告)日：2007-11-27

申请号：US10405958

申请日：2003-04-02

申请人： Nicolas Graciannette ,  Benoit Marchand

发明人： Nicolas Graciannette ,  Benoit Marchand

IPC分类号： G06F1/04

CPC分类号： G06F13/4217

摘要： A device is provided for synchronizing, on a reference clock signal, an exchange of data with a remote member. The device includes a main variable delay line controlled by a first processing unit coupled to a phase comparator in order to generate a delayed clock signal transmitted to the remote member. One input of the main variable delay line receives the reference clock signal. The device also includes a first terminal for receiving a clock signal image received by the remote member, a first auxiliary variable delay line having one input connected to the first terminal and one output connected to a first input of the phase comparator, a second auxiliary variable delay line having one input connected to the input of the main variable delay line and one output connected to a second input of the phase comparator, and a second processing unit controlling the first and second auxiliary variable delay lines so that the signal image received by the remote member is offset with respect to the reference clock signal, by a phase suitable for synchronizing the exchange of data on the reference clock signal.

摘要翻译： 提供了一种设备，用于在参考时钟信号上与远程成员进行数据交换。 该装置包括由连接到相位比较器的第一处理单元控制的主可变延迟线，以便产生发送给远程成员的延迟时钟信号。 主可变延迟线的一个输入端接收参考时钟信号。 该装置还包括用于接收由远程成员接收的时钟信号图像的第一终端，具有连接到第一终端的一个输入和连接到相位比较器的第一输入的一个输出的第一辅助可变延迟线，第二辅助变量 延迟线，其一个输入连接到主可变延迟线的输入，一个输出连接到相位比较器的第二输入，第二处理单元控制第一和第二辅助可变延迟线，使得由 远程成员相对于参考时钟信号偏移适合于同步参考时钟信号上的数据交换的相位。