公开(公告)号：US08819461B2

公开(公告)日：2014-08-26

申请号：US13335880

申请日：2011-12-22

申请人： Inder M. Sodhi ,  Alon Naveh ,  Michael Zelikson ,  Sanjeev s. Jahagirdar ,  Varghese George

发明人： Inder M. Sodhi ,  Alon Naveh ,  Michael Zelikson ,  Sanjeev s. Jahagirdar ,  Varghese George

IPC分类号： G06F1/00

CPC分类号： G06F1/3296 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D10/172

摘要： Embodiments of the invention relate to improving exit latency from computing device processor core deep power down. Processor state data may be maintained during deep power down mode by providing a secondary uninterrupted voltage supply to always on keeper circuits that reside within critical state registers of the processor. When these registers receive a control signal indicating that the processor power state is going to be reduced from an active processor power state to a zero processor power state, they write critical state data from the critical state register latches to the keeper circuits that are supplied with the uninterrupted power. Then, when a register receives a control signal indicating that a processor power state of the processor is going to be increased back to an active processor power state, the critical state data stored in the keeper circuits is written back to the critical state register latches.

摘要翻译： 本发明的实施例涉及从计算设备处理器核心深度掉电来改善退出等待时间。 处理器状态数据可以在深度掉电模式期间通过提供第二不间断电压供应来始终保持驻留在处理器的关键状态寄存器内的保持器电路。 当这些寄存器接收到指示处理器电源状态将从活动处理器电源状态降低到零处理器电源状态的控制信号时，它们将临界状态数据从临界状态寄存器锁存器写入到所提供的保持器电路 不间断的电源。 然后，当寄存器接收到指示处理器的处理器电源状态将增加回到活动处理器功率状态的控制信号时，存储在保持器电路中的临界状态数据被写回到临界状态寄存器锁存器。