Systems and methods for maximizing power efficiency of a digital power amplifier in a polar transmitter

    公开(公告)号:US10826738B2

    公开(公告)日:2020-11-03

    申请号:US16241842

    申请日:2019-01-07

    Applicant: Innophase Inc.

    Inventor: Jun Pan Yang Xu

    Abstract: A polar transmitter including a digital power amplifier cell that includes a first circuit and an amplifier circuit. The first circuit is configured to receive a phase modulated carrier signal and to generate a PMOS control signal and an NMOS control signal such that the PMOS control signal and the NMOS control signal have different duty cycles. The amplifier circuit is configured to receive the PMOS control signal at a PMOS transistor and the NMOS control signal at an NMOS transistor. The first circuit is configured to align the PMOS control signal and the NMOS control signal with respect to one another such that a time that the NMOS transistor and the PMOS transistor of the amplifier circuit are simultaneously conducting is minimized. The amplifier circuit is configured to generate an amplified modulated carrier signal in response to the PMOS and NMOS control signals.

    SYSTEMS AND METHODS FOR MAXIMIZING POWER EFFICIENCY OF A DIGITAL POWER AMPLIFIER IN A POLAR TRANSMITTER

    公开(公告)号:US20200220756A1

    公开(公告)日:2020-07-09

    申请号:US16241842

    申请日:2019-01-07

    Applicant: Innophase Inc.

    Inventor: Jun Pan Yang Xu

    Abstract: A polar transmitter including a digital power amplifier cell that includes a first circuit and an amplifier circuit. The first circuit is configured to receive a phase modulated carrier signal and to generate a PMOS control signal and an NMOS control signal such that the PMOS control signal and the NMOS control signal have different duty cycles. The amplifier circuit is configured to receive the PMOS control signal at a PMOS transistor and the NMOS control signal at an NMOS transistor. The first circuit is configured to align the PMOS control signal and the NMOS control signal with respect to one another such that a time that the NMOS transistor and the PMOS transistor of the amplifier circuit are simultaneously conducting is minimized. The amplifier circuit is configured to generate an amplified modulated carrier signal in response to the PMOS and NMOS control signals.

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