公开(公告)号：US20190018766A1

公开(公告)日：2019-01-17

申请号：US16070735

申请日：2016-08-09

Applicant: Institute of Computing Technology, Chinese Academy of Sciences

Inventor： Qi GUO ,  Tianshi CHEN ,  Yunji CHEN

IPC: G06F12/02

Abstract: The present disclosure may include a method that comprises: partitioning data on an on-chip and/or an off-chip storage medium into different data blocks according to a pre-determined data partitioning principle, wherein data with a reuse distance less than a pre-determined distance threshold value is partitioned into the same data block; and a data indexing step for successively loading different data blocks to at least one on-chip processing unit according a pre-determined ordinal relation of a replacement policy, wherein the repeated data in a loaded data block being subjected to on-chip repetitive addressing. Data with a reuse distance less than a pre-determined distance threshold value is partitioned into the same data block, and the data partitioned into the same data block can be loaded on a chip once for storage, and is then used as many times as possible, so that the access is more efficient.

公开(公告)号：US20190087716A1

公开(公告)日：2019-03-21

申请号：US16079525

申请日：2016-08-09

Applicant: Institute of Computing Technology, Chinese Academy of Sciences

Inventor： Zidong DU ,  Qi GUO ,  Tianshi CHEN ,  Yunji CHEN

IPC: G06N3/063 ,  G06F15/78 ,  G06F7/57

Abstract: The present disclosure provides a neural network processing system that comprises a multi-core processing module composed of a plurality of core processing modules and for executing vector multiplication and addition operations in a neural network operation, an on-chip storage medium, an on-chip address index module, and an ALU module for executing a non-linear operation not completable by the multi-core processing module according to input data acquired from the multi-core processing module or the on-chip storage medium, wherein the plurality of core processing modules share an on-chip storage medium and an ALU module, or the plurality of core processing modules have an independent on-chip storage medium and an ALU module. The present disclosure improves an operating speed of the neural network processing system, such that performance of the neural network processing system is higher and more efficient.

公开(公告)号：US20180321912A1

公开(公告)日：2018-11-08

申请号：US15773973

申请日：2016-06-17

Applicant: Institute of Computing Technology, Chinese Academy of Sciences

Inventor： Zhen LI ,  Shaoli LIU ,  Shijin ZHANG ,  Tao LUO ,  Cheng QIAN ,  Yunji CHEN ,  Tianshi CHEN

IPC: G06F7/509 ,  G06F17/30

CPC classification number: G06F7/5095 ,  G06F7/50 ,  G06F16/2246

Abstract: The present disclosure provides a data accumulation device and method, and a digital signal processing device. The device comprises: an accumulation tree module for accumulating input data in the form of a binary tree structure and outputting accumulated result data; a register module including a plurality of groups of registers and used for registering intermediate data generated by the accumulation tree module during an accumulation process and the accumulated result data; and a control circuit for generating a data gating signal to control the accumulation tree module to filter the input data not required to be accumulated, and generating a flag signal to perform the following control: selecting a result obtained after adding one or more of intermediate data stored in the register to the accumulated result as output data, or directly selecting the accumulated result as output data. Thus, a plurality of groups of input data can be rapidly accumulated to a group of sums in a clock cycle. At the same time, the accumulation device can flexibly select to simultaneously accumulate some data of the plurality of of input data by means of a control signal.