Abstract:
An integrated circuit chip is provided having a port for receiving a character string. A hardware hashing circuit on the integrated circuit chip is configured to perform a hashing function on the character string, thereby creating a hashed output value. A binary content addressable memory (CAM) array on the integrated circuit chip is coupled to receive the hashed output value. The binary CAM array provides an index value in response to the hashed output value if the hashed output value matches an entry of the binary CAM array. In a particular embodiment, the hardware hashing circuit can be configured to process character strings having different lengths (greater than the width of the binary CAM array) in response to one or more configuration bits. The hardware hashing circuit can include, an input register, Data Encryption Standard (DES) circuitry and exclusive OR circuitry.
Abstract:
A server is provided having a port for receiving a data request that includes an identifier (e.g., an HTTP request that includes a URL). Recognition logic is provided to extract the identifier, using delimiters present in the data request. Padding logic fixes the length of the identifier at a predetermined length (e.g., by adding zeros to the end of the identifier), thereby creating a fixed-length identifier. Hashing logic is provided to perform a hashing function on the fixed-length identifier, thereby creating a hashed identifier. A CAM array provides an index value in response to the hashed identifier if the hashed identifier matches a hashed identifier value stored in the CAM array. A cache memory stores information associated with the identifier (e.g., web page data), at a location associated with the index value. The cache memory provides this information to a requesting party in response to the index value.