公开(公告)号：US10672437B2

公开(公告)日：2020-06-02

申请号：US16357609

申请日：2019-03-19

Applicant: Integrated Device Technology, Inc.

Inventor： Steven E. Finn

IPC: G11C7/10 ,  H03D3/00 ,  H03G3/30 ,  H03K5/1536 ,  H04L27/156 ,  H04L25/06 ,  G11C7/22 ,  H03G1/00 ,  H03G1/04 ,  H04L1/20 ,  H04L25/03

Abstract: An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.

公开(公告)号：US20190296691A1

公开(公告)日：2019-09-26

申请号：US16357609

申请日：2019-03-19

Applicant: Integrated Device Technology, Inc.

Inventor： Steven E. Finn

IPC: H03D3/00 ,  H03G3/30 ,  H03K5/1536 ,  H04L27/156 ,  H04L25/06 ,  H04L25/03 ,  H03G1/00 ,  H03G1/04 ,  H04L1/20 ,  G11C7/10 ,  G11C7/22

Abstract: An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.