公开(公告)号：US20150268956A1

公开(公告)日：2015-09-24

申请号：US14659541

申请日：2015-03-16

Applicant: Intel Corporation

Inventor： KOICHI YAMADA ,  ALLAN M. KAY

IPC: G06F9/30 ,  G06F9/50 ,  G06F9/48

CPC classification number: G06F9/3009 ,  G06F9/3851 ,  G06F9/4843 ,  G06F9/5011 ,  G06F9/5077

Abstract: A processor including a plurality of logical processors, and an instruction set, the instruction set including of one or more instructions which when executed by a first logical processor, cause the first logical processor to make a processor execution resource previously reserved for the first processor available to a second processor in the plurality of processors in response to the first logical processor being scheduled to enter an idle state.

Abstract translation: 包括多个逻辑处理器的处理器和指令集，所述指令集包括一个或多个指令，当由第一逻辑处理器执行时，所述指令集使得所述第一逻辑处理器使得先前为所述第一处理器预留的处理器执行资源可用 响应于所述第一逻辑处理器被调度进入空闲状态而在所述多个处理器中的第二处理器。