公开(公告)号：US20160179520A1

公开(公告)日：2016-06-23

申请号：US14581435

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： ASHISH JHA ,  ROBERT VALENTINE ,  ELMOUSTAPHA OULD-AHMED-VALL

IPC: G06F9/30

CPC classification number: G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30072

Abstract: An apparatus and method for performing a variable mask-vector expand. For example, one embodiment of a processor comprises: a source mask register to store a plurality of mask bit values; an index register to store a plurality of index values each associated with a vector data element in a destination vector register and identifying a bit within the source mask register; and variable mask-vector expand logic to expand each of the mask bit values from the source mask register into the associated vector data elements using the index values from the index register, wherein all bits of a vector data element are to be set equal to the mask bit value identified by the index value associated with that vector data element.

Abstract translation: 一种用于执行可变掩码向量展开的装置和方法。 例如，处理器的一个实施例包括：源掩码寄存器，用于存储多个掩码位值; 索引寄存器，用于存储与目标向量寄存器中的向量数据元素相关联的多个索引值，并且识别源掩码寄存器内的位; 以及可变掩码向量扩展逻辑，以使用来自索引寄存器的索引值将源掩码寄存器中的每个掩码位值扩展到相关联的向量数据元素中，其中向量数据元素的所有位将被设置为等于 由与该向量数据元素相关联的索引值识别的掩码位值。

公开(公告)号：US20170177340A1

公开(公告)日：2017-06-22

申请号：US14977782

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： ASHISH JHA ,  ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  MARK J. CHARNEY ,  MILIND B. GIRKAR

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/3455

Abstract: A processor comprises a plurality of vector registers, and an execution unit, operatively coupled to the plurality of vector registers, the execution unit comprising a logic circuit implementing a load instruction for loading, into two or more vector registers, two or more data items associated with a data structure stored in a memory, wherein each one of the two or more vector registers is to store a data item associated with a certain position number within the data structure.

公开(公告)号：US20160179526A1

公开(公告)日：2016-06-23

申请号：US14581289

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： ASHISH JHA ,  ROBERT VALENTINE ,  ELMOUSTAPHA OULD-AHMED-VALL

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30043 ,  G06F9/30101 ,  G06F15/8053

Abstract: An apparatus and method for performing vector index loads and stores. For example, one embodiment of a processor comprises: a vector index register to store a plurality of index values; a mask register to store a plurality of mask bits; a vector register to store a plurality of vector data elements loaded from memory; and vector index load logic to identify an index stored in the vector index register to be used for a load operation using an immediate value and to responsively combine the index with a base memory address to determine a memory address for the load operation, the vector index load logic to load vector data elements from the memory address to the vector register in accordance with the plurality of mask bits.

Abstract translation: 用于执行向量索引加载和存储的装置和方法。 例如，处理器的一个实施例包括：矢量索引寄存器，用于存储多个索引值; 掩模寄存器，用于存储多个掩码位; 向量寄存器，用于存储从存储器加载的多个向量数据元素; 以及矢量索引负载逻辑，以识别存储在矢量索引寄存器中的索引，以用于使用立即值的加载操作，并且响应地将索引与基本存储器地址组合以确定用于加载操作的存储器地址，向量索引 负载逻辑，以根据多个掩码位将矢量数据元素从存储器地址加载到向量寄存器。

公开(公告)号：US20160179521A1

公开(公告)日：2016-06-23

申请号：US14581578

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： ASHISH JHA ,  ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE

IPC: G06F9/30

CPC classification number: G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30072

Abstract: An apparatus and method for performing a mask expand. For example, one embodiment of a processor comprises: a source mask register to store a plurality of mask values; mask expand logic to identify a first mask bit in the source mask register to be expanded using an index value and to determine a number of bit positions within a destination mask register into which the first mask bit is to be expanded using a second value, the mask expand logic to responsively copy the first mask bit to each of the determined bit positions within the destination mask register.

Abstract translation: 一种用于执行掩模扩展的装置和方法。 例如，处理器的一个实施例包括：源掩码寄存器，用于存储多个掩码值; 掩码扩展逻辑，以使用索引值来识别要被扩展的源掩码寄存器中的第一掩码位，并且使用第二值确定目标掩码寄存器中要扩展第一掩码位的位位数， 掩码扩展逻辑以将第一掩码位响应地复制到目的掩码寄存器中的每个确定的位位置。