公开(公告)号：US20200106413A1

公开(公告)日：2020-04-02

申请号：US16146095

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Brandon Davis ,  Aishwarya Balakrishnan

IPC: H03H7/21 ,  H03H7/06

Abstract: A polyphase filter operates to provide capacitive compensation to drive a multiphase network for generating quadrature signals. The polyphase filter can include a capacitive compensation mechanism at internal nodes. The capacitive compensation mechanism includes a first phase lag circuit between a first internal node and a second internal node and a second phase lag circuit coupled between a third internal node and a fourth internal node. The first internal node is coupled to the second internal node via a first inductor coupled to a first resistor, the second internal node is coupled to the third internal node via a second inductor coupled to a second resistor, the third internal node is coupled to the fourth internal node via a third inductor coupled to a third resistor, and the fourth internal node is coupled to the first internal node via a fourth inductor coupled to a fourth resistor.

公开(公告)号：US10734967B2

公开(公告)日：2020-08-04

申请号：US16146095

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Brandon Davis ,  Aishwarya Balakrishnan

IPC: H03H7/21 ,  H03H7/06 ,  H03H7/01

Abstract: A polyphase filter operates to provide capacitive compensation to drive a multiphase network for generating quadrature signals. The polyphase filter can include a capacitive compensation mechanism at internal nodes. The capacitive compensation mechanism includes a first phase lag circuit between a first internal node and a second internal node and a second phase lag circuit coupled between a third internal node and a fourth internal node. The first internal node is coupled to the second internal node via a first inductor coupled to a first resistor, the second internal node is coupled to the third internal node via a second inductor coupled to a second resistor, the third internal node is coupled to the fourth internal node via a third inductor coupled to a third resistor, and the fourth internal node is coupled to the first internal node via a fourth inductor coupled to a fourth resistor.