公开(公告)号：US20240143505A1

公开(公告)日：2024-05-02

申请号：US18393793

申请日：2023-12-22

Applicant: Intel Corporation

Inventor： Amruta MISRA ,  Ajay RAMJI ,  Rajendrakumar CHINNAIYAN ,  Chris MACNAMARA ,  Karan PUTTANNAIAH ,  Pushpendra KUMAR ,  Vrinda KHIRWADKAR ,  Sanjeevkumar Shankrappa ROKHADE ,  John J. BROWNE ,  Francesc GUIM BERNAT ,  Karthik KUMAR ,  Farheena Tazeen SYEDA

IPC: G06F12/0811

CPC classification number: G06F12/0811

Abstract: Methods and apparatus for dynamic selection of super queue size for CPUs with higher number of cores. An apparatus includes a plurality of compute modules, each module including a plurality of processor cores with integrated first level (L1) caches and a shared second level (L2) cache, a plurality of Last Level Caches (LLCs) or LLC blocks and a plurality of memory interface blocks interconnect via a mesh interconnect. A compute module is configured to arbitrate access to the shared L2 cache and enqueue L2 cache misses in a super queue (XQ). The compute module further is configured to dynamically adjust the size of the XQ during runtime operations. The compute module tracks parameters comprising an L2 miss rate or count and LLC hit latency and adjusts the XQ size as a function of these parameters. A lookup table using the L2 miss rate/count and LLC hit latency may be implemented to dynamically select the XQ size.