公开(公告)号：US20250107061A1

公开(公告)日：2025-03-27

申请号：US18372521

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Seenivasan SUBRAMANIAM ,  Anandkumar MAHADEVAN PILLAI

IPC: H10B10/00 ,  H01L23/528

Abstract: Structures having stacked transistors with backside access are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer including first, second, third and fourth stacks of nanowires and corresponding first, second, third and fourth overlying gate lines, and the device layer including first, second, third, fourth and fifth source or drain structures and corresponding overlying trench contacts alternating with the stacks of nanowires and the overlying gate lines, and one or more metallization layers above the device layer. A backside structure includes a backside via connection coupled to a bottom portion of the third source or drain structure, the bottom portion of the third source or drain structure isolated from a top portion of the third source or drain structure.