公开(公告)号：US12224015B2

公开(公告)日：2025-02-11

申请号：US17236651

申请日：2021-04-21

Applicant: Intel Corporation

Inventor： Ali Khakifirooz ,  Rezaul Haque ,  Dhanashree Kulkarni ,  Bayan Nasri

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26

Abstract: Systems, apparatuses and methods may provide for technology that applies a first set of control signals to even bitlines in NAND memory and senses voltage levels of the even bitlines during an even sensing time period. The technology may also apply a second set of control signals to odd bitlines in the NAND memory, and sense voltage levels of the odd bitlines during an odd sensing time period, wherein the second set of control signals are applied after expiration of a stagger time period between the even sensing time period and the odd sensing time period.

公开(公告)号：US20220343982A1

公开(公告)日：2022-10-27

申请号：US17236651

申请日：2021-04-21

Applicant: Intel Corporation

Inventor： Ali Khakifirooz ,  Rezaul Haque ,  Dhanashree Kulkarni ,  Bayan Nasri

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26

Abstract: Systems, apparatuses and methods may provide for technology that applies a first set of control signals to even bitlines in NAND memory and senses voltage levels of the even bitlines during an even sensing time period. The technology may also apply a second set of control signals to odd bitlines in the NAND memory, and sense voltage levels of the odd bitlines during an odd sensing time period, wherein the second set of control signals are applied after expiration of a stagger time period between the even sensing time period and the odd sensing time period.