公开(公告)号：US20240104049A1

公开(公告)日：2024-03-28

申请号：US18529363

申请日：2023-12-05

Applicant: Intel Corporation

Inventor： Erik Rijshouwer ,  Jeroen Leijten ,  Bert Schellekens ,  Zoran Zivkovic

IPC: G06F15/80 ,  G06F9/30

CPC classification number: G06F15/80 ,  G06F9/30098

Abstract: Techniques are disclosed for a programmable processor array architecture that enables synchronized broadcasting of operation results to register files with the operation results. The architecture advantageously enables writing of operation results of a given operation to multiple destination registers in a single clock cycle for processors with partitioned register files by using common data stationary instruction encoding. This combination brings improved performance by reducing the need for costly copy operations that would otherwise occupy issue slots and thus schedule space while at the same time minimizing code size overhead. The performance gains of broadcasting are especially emphasized in highly parallel and heavily partitioned register file architectures.