公开(公告)号：US20240311151A1

公开(公告)日：2024-09-19

申请号：US18120929

申请日：2023-03-13

Applicant: Intel Corporation

Inventor： Gilles Pokam ,  Andre Seznec ,  Jared Warner Stark, IV ,  Bhargav Reddy Godala

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/30047 ,  G06F9/3861 ,  G06F9/4881

Abstract: Techniques and mechanisms for prioritizing entries of a processor resource which is accessed to facilitate the fetching of an instruction for execution. In an embodiment, a first entry of the resource includes, or otherwise corresponds to, a version of the instruction. The first entry is prioritized based on an event wherein the instruction is retired from execution after a front end stall which is due to the instruction. While the first entry is prioritized, the entry is protected from a selection to be evicted from the resource. In another embodiment, second entries of a cache are variously prioritized, based on respective retirement events, to be available for instruction prefetching.