公开(公告)号：US20190026088A1

公开(公告)日：2019-01-24

申请号：US16070890

申请日：2016-02-23

Applicant: Intel Corporation

Inventor： Zhigang Gong ,  Wenqing Fu ,  Peng Li ,  Can Que ,  Zhiwen Wu

IPC: G06F8/41

Abstract: An input data structure of a first size may be converted to a plurality of data structures of a second size smaller than the first size. The data structures of the second size are realigned such that each of the plurality of data structures fits in one cache line. The realigned data structures are compiled for use in a vector machine.

公开(公告)号：US10761819B2

公开(公告)日：2020-09-01

申请号：US16070890

申请日：2016-02-23

Applicant: Intel Corporation

Inventor： Zhigang Gong ,  Wenqing Fu ,  Peng Li ,  Can Que ,  Zhiwen Wu

IPC: G06F8/41

Abstract: An input data structure of a first size may be converted to a plurality of data structures of a second size smaller than the first size. The data structures of the second size are realigned such that each of the plurality of data structures fits in one cache line. The realigned data structures are compiled for use in a vector machine.