公开(公告)号：US20240048543A1

公开(公告)日：2024-02-08

申请号：US18237754

申请日：2023-08-24

Applicant: Intel Corporation

Inventor： Ping Yu ,  Tomasz Kantecki ,  Chao Dou ,  Pablo De Lara Guarch ,  Brian Will

IPC: H04L9/40 ,  H04L69/22

CPC classification number: H04L63/0485 ,  H04L69/22

Abstract: An apparatus includes an interface to memory, and a processor to execute one or more instructions. The instructions cause the processor to receive, via an application programming interface (API), a plurality of packets, respective packets of the plurality of packets comprising a respective header and a respective payload. Further, the instructions cause the processor to determine, by a QUIC protocol stack, to encrypt the plurality of packets in parallel. Further, the instructions cause the processor to encrypt the payloads of the plurality of packets in parallel. Further, the instructions cause the processor to encrypt the headers of the plurality of packets in parallel.