公开(公告)号：US10223483B1

公开(公告)日：2019-03-05

申请号：US15390322

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Tat Hin Tan ,  William Walter Fergusson ,  Chieu Fung Tan

IPC: G06F17/50 ,  G06F11/34

Abstract: A methodology for defining resistance-capacitance (RC) design targets based on radio-frequency (RF) simulation is provided. In particular, the method may involve first determining capacitance targets and then determining resistance targets. To compute the capacitance targets, integrate circuit design and simulations tools may run transient analysis to identify critical nodes, perform small signal and sensitivity analysis for the capacitance on the critical nodes, revise original RF specifications by allocating additional margin, and perform interpolation among multiple capacitance values to obtain capacitive design targets that meet the revised specifications. To compute the resistance targets, the circuit design tools may identify critical transistors, run single-pass and DC operating point simulation to determine initial resistance values for the critical transistors, simplify parallel resistive networks, perform sensitivity analysis on the simplified networks, and perform interpolation among multiple resistive values to obtain resistive design targets meet the original RF performance specifications.