公开(公告)号：US09819258B1

公开(公告)日：2017-11-14

申请号：US15283084

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Clark Vandam ,  Suriya Kumar ,  Suraj Sindia ,  Ricardo Ascazubi ,  Curtis Shirota

IPC: H03K19/003 ,  H02M1/32 ,  H02M1/36 ,  G11C5/14

CPC classification number: G01R31/31816

Abstract: Systems and methods for latch-up detection and mitigation. One aspect includes a method implemented in a system divided into a plurality of power blocks, where each power block is powered by a corresponding power rail and includes a voltage droop monitoring circuitry. The method comprises receiving frequency information from the plurality of voltage droop monitoring circuitries; normalizing the received frequency information from each of the plurality of voltage droop monitoring circuitries; creating a matrix of cross-correlation values based on the normalized frequency information between each pair of the plurality of power blocks; determining deviations in the cross-correlation values indicating an occurrence of voltage droop; determining an abnormal variation based on the determined deviations to identify a first power block, out of the plurality of power blocks, experiencing a latch-up event; and resetting power to the first power block without interrupting power to rest of the plurality of power blocks.