公开(公告)号：US20240354057A1

公开(公告)日：2024-10-24

申请号：US18523186

申请日：2023-11-29

Applicant: Intel Corporation

Inventor： Jongwook Sohn ,  David Dean ,  Eric Quintana ,  Wing Shek Wong

IPC: G06F7/523

CPC classification number: G06F7/523

Abstract: Techniques and mechanisms for circuitry to support the performance of a fused multiply-add (FMA) operation with one or more denormal numbers. In some embodiments, a processor is operable to execute a FMA instruction comprising or otherwise identifying two multiplicands, and an addend. Such execution includes performing one-way alignment of an addend significand based on a difference between respective exponent values of the two multiplicands. The alignment is performed in parallel with operations by a multiplier circuit based on respective significand values of the two multiplicands. Subtraction of a J-bit correction value is performed in the multiplier circuit to avoid mitigate execution delay. In another embodiment, first circuitry of a processor executes an FMA instruction, wherein components of the first circuitry are shared with second circuitry of the processor, and wherein the second circuitry supports the execution of a floating-point multiplication instruction.