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公开(公告)号：US20210306155A1
公开(公告)日：2021-09-30
申请号：US16830844
申请日：2020-03-26
Applicant: Intel Corporation
Inventor： Manoj Sastry , Rafael Misoczki , Jordan Loney , David M. Wheeler
Abstract: In one example an apparatus comprises a computer readable memory, a signing facility comprising a plurality of hardware security modules, and a state synchronization manager comprising processing circuitry to select, from the plurality of hardware security modules, a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module, and assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence. Other examples may be described.
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公开(公告)号：US11750403B2
公开(公告)日：2023-09-05
申请号：US17816148
申请日：2022-07-29
Applicant: Intel Corporation
Inventor： Manoj Sastry , Rafael Misoczki , Jordan Loney , David M. Wheeler
CPC classification number: H04L9/3247 , G06F21/72 , H04L9/3236
Abstract: In one example an apparatus comprises a computer readable memory, a signing facility comprising a plurality of hardware security modules, and a state synchronization manager comprising processing circuitry to select, from the plurality of hardware security modules, a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module, and assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence. Other examples may be described.
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公开(公告)号：US11438172B2
公开(公告)日：2022-09-06
申请号：US16830844
申请日：2020-03-26
Applicant: Intel Corporation
Inventor： Manoj Sastry , Rafael Misoczki , Jordan Loney , David M. Wheeler
Abstract: In one example an apparatus comprises a computer readable memory, a signing facility comprising a plurality of hardware security modules, and a state synchronization manager comprising processing circuitry to select, from the plurality of hardware security modules, a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module, and assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence. Other examples may be described.
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公开(公告)号：US20220368537A1
公开(公告)日：2022-11-17
申请号：US17816148
申请日：2022-07-29
Applicant: Intel Corporation
Inventor： Manoj Sastry , Rafael Misoczki , Jordan Loney , David M. Wheeler
Abstract: In one example an apparatus comprises a computer readable memory, a signing facility comprising a plurality of hardware security modules, and a state synchronization manager comprising processing circuitry to select, from the plurality of hardware security modules, a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module, and assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence. Other examples may be described.
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