公开(公告)号：US20190318130A1

公开(公告)日：2019-10-17

申请号：US16456308

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Debayan Das ,  Carlos Tokunaga ,  Avinash L. Varna ,  Joseph Friel

IPC: G06F21/72 ,  G06F21/64 ,  G06F21/12

Abstract: Embodiments are directed to countermeasures against hardware side-channel attacks on cryptographic operations. An embodiment of an apparatus includes multiple crypto cores; and a current source including multiple current source blocks, the current source blocks including a respective current source block associated with each of the crypto cores, and wherein the current sources blocks are switchable to switch on a current source block associated with each active core of the multiple crypto cores and to switch off a current source associated with each inactive core of the multiple cryptographic cores.

公开(公告)号：US20250005209A1

公开(公告)日：2025-01-02

申请号：US18343609

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Debayan Das ,  Santosh Ghosh ,  Manoj Sastry

IPC: G06F21/75

Abstract: Techniques for attenuation and obfuscation to mitigate power and/or electromagnetic (EM) field attacks on encryption circuitry are described. In certain examples, a system includes a processor core; and an accelerator coupled to the processor core, the accelerator comprising: encryption circuitry, coupled to a power source, to encrypt data into encrypted data, time-domain obfuscation control circuitry to connect and disconnect one or more capacitors to the encryption circuitry during the encrypt to provide obfuscation across a time-domain to maintain a software observable power consumption of the accelerator to about a value, and signature attenuation control circuitry to selectively connect the encryption circuitry during the encrypt to a shunt to drain power to maintain the software observable power consumption of the accelerator at about the value.

公开(公告)号：US20240129104A1

公开(公告)日：2024-04-18

申请号：US17964549

申请日：2022-10-12

Applicant: Intel Corporation

Inventor： Jason M. Fung ,  Debayan Das ,  Sayak Ray ,  Rana Elnaggar ,  Majid Sabbagh

IPC: H04L9/00

CPC classification number: H04L9/003

Abstract: An apparatus, system, and method for protecting a component from an observation attack are provided. A power balancing circuit configured to protect a cryptography component can include a ring oscillator electrically connected to a power supply, a time-to-digital converter (TDC) electrically connected to monitor an electrical parameter of the electrical power drawn by the cryptography component and provide data indicative of the electrical parameter, and a controller circuit configured to adjust a number of inverters of the ring oscillator drawing power from the power supply based on the data.

公开(公告)号：US11216594B2

公开(公告)日：2022-01-04

申请号：US16456308

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Debayan Das ,  Carlos Tokunaga ,  Avinash L. Varna ,  Joseph Friel

IPC: G06F21/72 ,  G06F21/12 ,  G06F21/64

Abstract: Embodiments are directed to countermeasures against hardware side-channel attacks on cryptographic operations. An embodiment of an apparatus includes multiple crypto cores; and a current source including multiple current source blocks, the current source blocks including a respective current source block associated with each of the crypto cores, and wherein the current sources blocks are switchable to switch on a current source block associated with each active core of the multiple crypto cores and to switch off a current source associated with each inactive core of the multiple cryptographic cores.