公开(公告)号：US20210200667A1

公开(公告)日：2021-07-01

申请号：US16727595

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Debra BERNSTEIN ,  Hugh WILKINSON ,  Douglas CARRIGAN ,  Bassam N. COURY ,  Matthew J. ADILETTA ,  Durgesh SRIVASTAVA ,  Lidia WARNES ,  William WHEELER ,  Michael F. FALLON

IPC: G06F12/02 ,  G06F3/06

Abstract: Examples described herein relate to memory thin provisioning in a memory pool of one or more dual in-line memory modules or memory devices. At any instance, any central processing unit (CPU) can request and receive a full virtual allocation of memory in an amount that exceeds the physical memory attached to the CPU (near memory). A remote pool of additional memory can be dynamically utilized to fill the gap between allocated memory and near memory. This remote pool is shared between multiple CPUs, with dynamic assignment and address re-mapping provided for the remote pool. To improve performance, the near memory can be operated as a cache of the pool memory. Inclusive or exclusive content storage configurations can be applied. An inclusive cache configuration can include an entry in a near memory cache also being stored in a memory pool whereas an exclusive cache configuration can provide an entry in either a near memory cache or in a memory pool but not both. Near memory cache management includes current data location tracking, access counting and other caching heuristics, eviction of data from near memory cache to pool memory and movement of data from pool memory to memory cache.

公开(公告)号：US20210117249A1

公开(公告)日：2021-04-22

申请号：US17134324

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Kshitij A. DOSHI ,  Johan VAN DE GROENENDAAL ,  Edmund CHEN ,  Ravi SAHITA ,  Andrew J. HERDRICH ,  Debra BERNSTEIN ,  Christine E. SEVERNS-WILLIAMS ,  Uri V. CUMMINGS ,  Utkarsh Y. KAKAIYA

IPC: G06F9/52 ,  H04L29/08

Abstract: Examples described herein relate to an Infrastructure Processing Unit (IPU) that comprises: interface circuitry to provide a communicative coupling with a platform; network interface circuitry to provide a communicative coupling with a network medium; and circuitry to expose infrastructure services to be accessed by microservices for function composition and to selectively provide a barrier to halt operation of at least one microservice based on event data from a composite node that performs the at least one microservice.

公开(公告)号：US20210117242A1

公开(公告)日：2021-04-22

申请号：US17134321

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Johan VAN DE GROENENDAAL ,  Kshitij A. DOSHI ,  Edmund CHEN ,  Ravi SAHITA ,  Andrew J. HERDRICH ,  Debra BERNSTEIN ,  Christine E. SEVERNS-WILLIAMS ,  Uri V. CUMMINGS ,  Utkarsh Y. KAKAIYA

IPC: G06F9/50 ,  H04L29/08 ,  G06F9/54 ,  H04L12/26

Abstract: Examples described herein relate to an Infrastructure Processing Unit (IPU) that comprises: interface circuitry to provide a communicative coupling with a platform; network interface circuitry to provide a communicative coupling with a network medium; and circuitry to expose infrastructure services to be accessed by microservices for function composition.