公开(公告)号：US20210325956A1

公开(公告)日：2021-10-21

申请号：US17359403

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Virendra Vikramsinh ADSURE ,  Chia-Hung S. KUO ,  Robert J. ROYER, JR. ,  Deepak GANDIGA SHIVAKUMAR

IPC: G06F1/3293

Abstract: Examples include techniques to reduce memory power consumption during a system idle state. Cores of a single socket multi-core processor may be mapped to different virtual non-uniform memory architecture (NUMA) nodes and a dynamic random access memory (DRAM) may be partitioned into multiple segments that are capable of having self-refresh operations separately deactivated or activated. Different segments from among the multiple segments of DRAM may be mapped to the virtual NUMA nodes to allow for a mechanism to cause memory requests for pinned or locked pages of data to be directed to a given virtual NUMA node.

公开(公告)号：US20250110812A1

公开(公告)日：2025-04-03

申请号：US18979399

申请日：2024-12-12

Applicant: Intel Corporation

Inventor： Yingqi LU ,  Smita KUMAR ,  Tracy Garrett DRYSDALE ,  Ranjit MENON ,  Toby OPFERMAN ,  Deepak GANDIGA SHIVAKUMAR ,  Stephen DOYLE ,  Corey D. GOUGH

IPC: G06F9/54

Abstract: Examples described herein relate to a processor to execute the instructions to cause: issue a first call to an application program interface (API) to an accelerator to cause the accelerator to compress data. In some examples, the API is to indicate whether the data is to be preserved in a buffer. In some examples, the API is to indicate a first offset. In some examples, the accelerator is to store the data starting at an address that is the first offset from a beginning address of the buffer allocated in a memory device. In some examples, the accelerator is to store the compressed data starting at a second offset from the beginning address of the buffer while the data is also stored in the buffer.