公开(公告)号：US20220197635A1

公开(公告)日：2022-06-23

申请号：US17132464

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Deepti AGGARWAL ,  Michael ESPIG ,  Chekib NOUIRA ,  Robert VALENTINE ,  Mark CHARNEY

IPC: G06F9/30 ,  G06F17/16 ,  G06F17/18 ,  G06F9/38

Abstract: In an embodiment, a processor includes: a fetch circuit to fetch instructions, the instructions including a sum of squared differences (SSD) instruction; a decode circuit to decode the SSD instruction; and an execution circuit to, during an execution of the decoded SSD instruction, generate an SSD output vector based on a plurality of input vectors, the SSD output vector including a plurality of squared differences values. Other embodiments are described and claimed.

公开(公告)号：US20250028533A1

公开(公告)日：2025-01-23

申请号：US18224919

申请日：2023-07-21

Applicant: Intel Corporation

Inventor： John MORGAN ,  Michael ESPIG ,  Deepti AGGARWAL

IPC: G06F9/30

Abstract: Techniques for zero clearing scalar moves are described. For example, one or more instructions are supported which, when executed, are to cause a scalar move of a 16-bit or 32-bit floating-point value from a source to a destination. When the destination is a vector register, all other data elements are to be zeroed.