公开(公告)号：US20190121658A1

公开(公告)日：2019-04-25

申请号：US16226367

申请日：2018-12-19

Applicant: Intel Corporation

Inventor： Arumugam THIYAGARAJAH ,  Rajesh SANKARAN ,  Dharmendra THAKKAR

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/455

Abstract: A processor includes a processor core, a processor cache to store reporting data structures including a queue structure, and an interrupt posting circuit coupled to the processor core and the processing cache. The interrupt posting circuit receives an interrupt request directed to a virtual processor (VP) of a virtual machine (VM) executed by the processor core. The VM is managed by a virtual machine monitor (VMM) executed by the processor core. The interrupt posting circuit determines the VP is in an inactive state and records the interrupt request in a first posted data structure allocated by the VMM for the VP in main memory coupled to the processor. The interrupt posting circuit updates location information stored in the reporting data structures based on recording the interrupt request in the first posted data structure to generate updated location information that identifies a location of the interrupt request.