公开(公告)号：US20210382754A1

公开(公告)日：2021-12-09

申请号：US17406711

申请日：2021-08-19

Applicant: Intel Corporation

Inventor： Yamini Nimmagadda ,  Akhila Vidiyala ,  Suryaprakash Shanmugam ,  Divya Prakash

IPC: G06F9/50 ,  G06N3/08

Abstract: Systems, apparatuses and methods include technology that analyzes an input stream and an artificial intelligence (AI) model graph to generate a workload characterization. The workload characterization characterizes one or more of compute resources or memory resources, and the one or more of the compute resources or the memory resources is associated with execution of the AI model graph based on the input stream. The technology partitions the AI model graph into subgraphs based on the workload characterization. The technology selects a plurality of hardware devices to execute the subgraphs.

公开(公告)号：US12106154B2

公开(公告)日：2024-10-01

申请号：US17406711

申请日：2021-08-19

Applicant: Intel Corporation

Inventor： Yamini Nimmagadda ,  Akhila Vidiyala ,  Suryaprakash Shanmugam ,  Divya Prakash

IPC: G06F9/46 ,  G06F9/50 ,  G06N3/08

CPC classification number: G06F9/505 ,  G06F9/5016 ,  G06F9/5072 ,  G06N3/08

Abstract: Systems, apparatuses and methods include technology that analyzes an input stream and an artificial intelligence (AI) model graph to generate a workload characterization. The workload characterization characterizes one or more of compute resources or memory resources, and the one or more of the compute resources or the memory resources is associated with execution of the AI model graph based on the input stream. The technology partitions the AI model graph into subgraphs based on the workload characterization. The technology selects a plurality of hardware devices to execute the subgraphs.

公开(公告)号：US20210390460A1

公开(公告)日：2021-12-16

申请号：US17459141

申请日：2021-08-27

Applicant: Intel Corporation

Inventor： Yamini Nimmagadda ,  Suryaprakash Shanmugam ,  Akhila Vidiyala ,  Divya Prakash

IPC: G06N20/00 ,  G06K9/62 ,  G06F9/50

Abstract: Systems, apparatuses and methods include technology that converts an artificial intelligence (AI) model graph into an intermediate representation. The technology partitions the intermediate representation of the AI model graph into a plurality of subgraphs based on computations associated with the AI model graph, each subgraph being associated with one or more memory resources and one or more of a plurality of hardware devices. The technology determines whether to readjust the plurality of subgraphs based on the memory resources associated with the plurality of subgraphs and memory capacities of the plurality of hardware devices