公开(公告)号：US20190080257A1

公开(公告)日：2019-03-14

申请号：US15699860

申请日：2017-09-08

Applicant: Intel Corporation

Inventor： LI CHEN ,  ERDEM AKTAS

IPC: G06N99/00 ,  G06N5/04 ,  G06N7/00

Abstract: One embodiment provides a system including processor, a storage device, training logic and runtime prediction logic to develop a model to enable improved checkpointing. The training logic trains the model using simulated or known data to predict a size of a changelog needed for checkpointing. The size of the changelog is correlated to user type and timespan (as a checkpoint tracking changes made over a full week is likely larger than a checkpoint tracking changes made over a single day, and some types of users make more changes than others). Thus, the training logic utilizes sample data corresponding to various user types and timespans to train and validate the model for various combinations. Once the model is trained, the training logic may send the trained model to the runtime prediction model for use during operation of the system. During operation, the runtime prediction logic uses the model to predict a size of a reserved area where the changelog will be stored. The runtime prediction logic also monitors actual use of the reserved area during operation over time (e.g., tracks the size of the changelog as it grows) and compares the changelog size to the predictions from the model. The runtime prediction logic revises the model as needed based on the actual use. Thus, the system improves checkpointing by reducing wasted space.