公开(公告)号：US20200089494A1

公开(公告)日：2020-03-19

申请号：US16579394

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Asit K. MISHRA ,  Edward T. GROCHOWSKI ,  Jonathan D. PEARCE ,  Deborah T. MARR ,  Ehud COHEN ,  Elmoustapha OULD-AHMED-VALL ,  Jesus Corbal SAN ADRIAN ,  Robert VALENTINE ,  Mark J. CHARNEY ,  Christopher J. HUGHES ,  Milind B. GIRKAR

IPC: G06F9/30

Abstract: A processor includes a decode unit to decode an instruction that is to indicate a first source packed data operand that is to include at least four data elements, to indicate a second source packed data operand that is to include at least four data elements, and to indicate one or more destination storage locations. The execution unit, in response to the instruction, is to store at least one result mask operand in the destination storage location(s). The at least one result mask operand is to include a different mask element for each corresponding data element in one of the first and second source packed data operands in a same relative position. Each mask element is to indicate whether the corresponding data element in said one of the source packed data operands equals any of the data elements in the other of the source packed data operands.