公开(公告)号：US20180367147A1

公开(公告)日：2018-12-20

申请号：US15625897

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Kok Wah Khor ,  Eng Ling Ho

IPC: H03K19/177

CPC classification number: H03K19/17756 ,  H03K19/1776

Abstract: A system may include a host processor and a coprocessor for accelerating tasks received from the host processor. The coprocessor may include programmable circuitry organized into logic sectors. Each logic sector may have a dedicated local sector manager (LSM). The LSMs may be controlled by a secure device manager (SDM). The SDM may be coupled to data unloading circuitry for unloading configuration data from the coprocessor off onto the host processor. The unloading circuitry may include a circular first-in first-out (FIFO) buffer circuit that can be divided into multiple partitions to store configuration data from the various LSMs. The FIFO buffer circuit may be configured as an input FIFO in a configuration (loading) mode or as an output FIFO in a data unloading mode.

公开(公告)号：US10218358B2

公开(公告)日：2019-02-26

申请号：US15625897

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Kok Wah Khor ,  Eng Ling Ho

IPC: H03K19/177

Abstract: A system may include a host processor and a coprocessor for accelerating tasks received from the host processor. The coprocessor may include programmable circuitry organized into logic sectors. Each logic sector may have a dedicated local sector manager (LSM). The LSMs may be controlled by a secure device manager (SDM). The SDM may be coupled to data unloading circuitry for unloading configuration data from the coprocessor off onto the host processor. The unloading circuitry may include a circular first-in first-out (FIFO) buffer circuit that can be divided into multiple partitions to store configuration data from the various LSMs. The FIFO buffer circuit may be configured as an input FIFO in a configuration (loading) mode or as an output FIFO in a data unloading mode.

公开(公告)号：US20190342141A1

公开(公告)日：2019-11-07

申请号：US16421208

申请日：2019-05-23

Applicant: Intel Corporation

Inventor： Eng Ling Ho ,  Sean Atsatt ,  Chiew Siang Wong ,  Chin Hai Ang ,  Rob Pelt ,  EE Mei Ooi

IPC: H04L12/24 ,  H04L29/08

Abstract: Methods and systems for configuring a programmable logic device include receiving configuration data at an input of a first sector of the programmable logic device and dynamically routing the configuration data through the first sector to a second sector of the programmable device by selecting a first routing path out of the first sector or a second routing path out of the first sector.

公开(公告)号：US10938620B2

公开(公告)日：2021-03-02

申请号：US16421208

申请日：2019-05-23

Applicant: Intel Corporation

Inventor： Eng Ling Ho ,  Sean Atsatt ,  Chiew Siang Wong ,  Chin Hai Ang ,  Rob Pelt ,  Ee Mei Ooi

IPC: H04L12/24 ,  H04L29/08

Abstract: Methods and systems for configuring a programmable logic device include receiving configuration data at an input of a first sector of the programmable logic device and dynamically routing the configuration data through the first sector to a second sector of the programmable device by selecting a first routing path out of the first sector or a second routing path out of the first sector.

公开(公告)号：US10355909B1

公开(公告)日：2019-07-16

申请号：US15438228

申请日：2017-02-21

Applicant: Intel Corporation

Inventor： Eng Ling Ho ,  Sean Atsatt ,  Chiew Siang Wong ,  Chin Hai Ang ,  Rob Pelt ,  Ee Mei Ooi

IPC: H04L12/24 ,  H04L29/08

Abstract: Methods and systems for configuring a programmable logic device include receiving configuration data at an input of a first sector of the programmable logic device and dynamically routing the configuration data through the first sector to a second sector of the programmable device by selecting a first routing path out of the first sector or a second routing path out of the first sector.