公开(公告)号：US20210232426A1

公开(公告)日：2021-07-29

申请号：US17094412

申请日：2020-11-10

Applicant: Intel Corporation

Inventor： Andrew Herdrich ,  Ian Steiner ,  Leeor Peled ,  Michael Prinke ,  Eylon Toledano

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/54

Abstract: A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.

公开(公告)号：US20200310865A1

公开(公告)日：2020-10-01

申请号：US16370248

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Andrew Herdrich ,  Ian Steiner ,  Leeor Peled ,  Michael Prinke ,  Eylon Toledano

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/54

Abstract: A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.