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公开(公告)号：US20220326860A1
公开(公告)日：2022-10-13
申请号：US17850455
申请日：2022-06-27
Applicant: Intel Corporation
Inventor： Jun LI , Subhankar PANDA , Gaurav PORWAL , Feiting WANYAN
IPC: G06F3/06
Abstract: A dedicated bank-based error counter is provided for a respective bank of a Dynamic Random Access Memory (DRAM). The dedicated bank-based error counter for the bank is stored in memory resources. A Basic Input/Output System (BIOS) System Management Interrupt (SMI) handler triggers Adaptive Double Device Data Correction (ADDDC) bank sparing if the error count for the respective bank equals or exceeds a per bank ADDDC threshold.
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