公开(公告)号：US20180314289A1

公开(公告)日：2018-11-01

申请号：US15499936

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： RAJSHREE A. CHABUKSWAR ,  MICHAEL W. CHYNOWETH ,  ELIEZER WEISSMANN ,  JEREMY J. SHRALL ,  GREG D. KAINE

IPC: G06F1/12 ,  G06F1/08 ,  G06F9/48 ,  G06F9/30

Abstract: A processor includes a plurality of processing engines and a throttling circuit. The throttling circuit may be to: detect an execution of a pause instruction in a first processing engine operating at a first frequency level; in response to the execution of the pause instruction, increment a cycle counter to count a number of cycles that the first processing engine is paused by executing the pause instruction; and in response to a determination that the cycle counter has reached a first threshold level, change an operating frequency of the first processing engine from the first frequency level to a second frequency level, wherein the second frequency level is lower than the first frequency level.