公开(公告)号：US20190213289A1

公开(公告)日：2019-07-11

申请号：US16356713

申请日：2019-03-18

Applicant: Intel Corporation

Inventor： Gregg William BAECKLER ,  Martin LANGHAMMER ,  Sergey GRIBOK ,  Scott J. WEBER ,  Gregory STEINKE

IPC: G06F17/50 ,  G06F1/03 ,  G06F9/445

CPC classification number: G06F17/505 ,  G06F1/03 ,  G06F9/44505 ,  G06F17/5054

Abstract: A method for designing a system on a target device is disclosed. The system is synthesized from a register transfer level description. The system is placed on the target device. The system is routed on the target device. A configuration file is generated that reflects the synthesizing, placing, and routing of the system for programming the target device. A modification for the system is identified. The configuration file is modified to effectuate the modification for the system without changing the placing and routing of the system.

公开(公告)号：US20190121927A1

公开(公告)日：2019-04-25

申请号：US16218179

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： Martin LANGHAMMER ,  Sergey GRIBOK ,  Gregg William BAECKLER

IPC: G06F17/50 ,  H03K19/177

Abstract: A method for implementing a multiplier on a programmable logic device (PLD) is disclosed. Partial product bits of the multiplier are identified and how the partial product bits are to be summed to generate a final product from a multiplier and multiplicand are determined. Chains of PLD cells and cells in the chains of PLD cells for generating and summing the partial product bits are assigned. It is determined whether a bit in an assigned cell in an assigned chain of PLD cells is under-utilized. In response to determining that a bit is under-utilized, the assigning of the chains of PLD cells and cells for generating and summing the partial product bits are changed to improve an overall utilization of the chains of PLD cells and cells in the chains of PLD cells.

公开(公告)号：US20190042683A1

公开(公告)日：2019-02-07

申请号：US16022857

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Martin LANGHAMMER ,  Gregg William BAECKLER ,  Sergey GRIBOK

IPC: G06F17/50

Abstract: A method for designing and configuring a system on a field programmable gate array (FPGA) is disclosed. A portion of the system that is implemented greater than a predetermined number of times is identified. A structural netlist that describes how to implement the portion of the system a plurality of times on the FPGA and that leverages a repetitive nature of implementing the portion is generated. The identifying and generating is performed prior to synthesizing and placing other portions of the system that are not implemented greater than the predetermined number of time. Synthesizing, placing, and routing the other portions of the system on the FPGA is performed in accordance with the structural netlist. The FPGA is configured with a configuration file that includes a design for the system that reflects the synthesizing, placing, and routing, wherein the configuring physically transforms resources on the FPGA to implement the system.